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Placement and routing for video Codec applications running on modern FPGAs

Placement and routing for video Codec applications running on modern FPGAs
现代 FPGA 上运行的视频编解码器应用的布局和布线
批准号:
530734-2018
负责人:
Grewal, Gary
金额:
$1.82万
依托单位:
依托单位国家:
加拿大
项目类别:
Engage Grants Program
财政年份:
2018
资助国家:
加拿大
项目状态:
已结题
起止时间:
2018-01-01 至 2019-12-31

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中文摘要
翻译
每天,仅YouTube的浏览者就观看近50亿个视频。此外,据估计,近64%的互联网流量是视频内容,预计到2019年这一数字将上升到80%。在这种情况下,视频编码和视频压缩都是关键的启用技术。它们不仅允许视频以更小的方式传输,需要更少的带宽和更少的存储空间,而且还可以为更多的个人提供访问视频内容的机会。随着不断扩展的显示分辨率和不断发展的压缩,**需要高性能,低成本,可重新编程的硬件架构,可以快速升级**。现场可编程门阵列(fpga)非常适合满足这些需求。fpga融合了软件和硬件的优点,提供比软件更大的功率,面积和性能优势,但它们可以廉价地重新编程以满足许多视频和图像处理应用的要求。在本提案中,我们将探索将视频处理应用映射到现代FPGA设备上的方法,以实现应用的最大性能。特别是,将开发几个工具来帮助在映射过程的放置阶段。这些工具将包括适合将设计中的功能块放置在FPGA上的合法位置的优化,以减少带宽和拥塞,并改善时序。我们将针对两种适合满足视频应用要求的FPGA架构:一种是在单个芯片上包含所有硬件资源,另一种是在三个芯片上包含这些资源。由此产生的工具将有助于支持基于fpga的视频和图像处理应用。
英文摘要
Each day, YouTube viewers alone watch almost 5 billion videos. Moreover, it is estimated that almost 64% of**all internet traffic is video content, with this number expected to rise to 80% by 2019. Both video encoding and**video compression are key enabling technologies in this context. Not only do they allow video to be delivered**in smaller bundles requiring less bandwidth and less storage, they also make it possible to provide many more**individuals with access to video content. With ever expanding display resolutions and evolving compression,**there is a need for high performance, low cost, reprogrammable hardware architectures that can be upgraded**quickly. Field Programmable Gate Arrays (FPGAs) are well suited to meet these needs. FPGAs blend the**benefits of both software and hardware, providing huge power, area, and performance benefits over software,**yet they can be reprogrammed cheaply to meet the requirements of many video and image processing**applications. In this proposal, we will explore ways of mapping video processing applications onto a modern**FPGA device to achieve maximum performance from the application. In particular, several tools will be**developed to help during the placement phase of the mapping process. These tools will consist of optimizations**suitable for placing the functional blocks in a design onto legal locations on an FPGA in a way that reduces**wirelength and congestion, and improves timing. We will target two types of FPGA architectures suitable for**meeting the requirements of video applications: one that contains all of the hardware resources on a single die,**and another that contains these resources on three dies. The resulting tools will help to support FPGA-based**video and image processing applications.
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