High Performance Deep Scaled CMOS Transceivers

本研究的目的是推进单片无线电电路的艺术。作者制作的窄带通信电路现已投入工业生产。此外，他还从事宽带相控阵无线通信电路和全数字锁相环路（adpll）的研究，这些电路可用于计算机系统中的无线和局域网。这包括完整的射频和模拟无线电子系统，前端工作，频率合成和模拟/数字转换电路。通过集成所有三个领域的工作，他可以做出适当的权衡，并利用系统组件之间的协同作用。这项工作的主要重点是通过晶体管通道长度远低于100nm的低成本深度CMOS技术获得高性能。正在开发的两种新技术是低功率/相位噪声注入锁定振荡器和低抖动/高线性次采样电路，可用于接收数据并作为次采样合成器的一部分。最近，这些技术已被集成为毫米波相控阵架构的一部分，并作为注入锁定旋转行波振荡器的一部分，提供卓越的性能和低功耗。特别是，这些实现的最先进的相位噪声性能解决了高数据速率无线系统的一个关键限制。这项工作的意义在于能够生产具有数据速率能力的低成本高集成CMOS收发器，以支持流媒体视频和千兆无线数据网络等最苛刻的应用。***这项工作的一个关键方面将是开发高频低相位振荡器和合成器，它们通常是使用高阶调制信号的无线收发器的限制因素。同样关键的是在深度缩放CMOS技术中实现这些电路的能力，并在不降低性能或大大增加功耗的情况下将其信号分布在整个IC中。作者对早期的结果感到鼓舞，并注意到该技术在雷达系统，片上时钟分配网络和高性能SERDES电路中具有更广泛的应用

The objective of this research is to advance the art of monolithic radio circuits. The author has produced circuits now in industrial production for narrow band communications. As well, he is working on broadband phased array wireless communications circuits and All Digital Phase-Lock Loop Circuits (ADPLLs) that can be used for both wireless and local area networking in computer systems. This includes the complete RF and analog radio subsystem, with work on front-end, frequency synthesis and analog/digital conversion circuits. By integrating efforts in all three areas, he can make proper tradeoffs and exploit synergies between system components.***The main focus of this effort is directed at getting high performance from low-cost deep scaled CMOS technologies with transistor channel lengths well below 100nm. Two novel technologies being developed are low power/phase noise injection locked oscillators and low jitter/high linearity subsampling circuits that can be used for receiving data and as part of a subsampling synthesizer. Most recently, these technologies have been integrated as part of millimeter wave phased array architecture and as part of an Injection Locked Rotary Travelling Wave Oscillator which provide superior performance with low power consumption. In particular, the state of the art phase noise performance of these implementations addresses one of the key limitations of high data rate wireless systems. The significance of this work will be the ability to produce low cost highly integrated CMOS transceivers with data rates capabilities to support the most demanding applications such as streaming video and gigabit wireless data networks.***One of the critical aspects of this work will be developing high frequency low phase oscillators and synthesizers which are typically the limiting factor in wireless transceivers using higher order modulation signals. Also critical is the ability to implement these circuits in deep scaled CMOS technologies and distribute their signals throughout an IC without degrading performance or greatly increasing power consumption. The author is encouraged by early results and would note that this technology has broader applications in radar systems, on-chip clock distribution networks and high performance SERDES circuits.**