Avalanche Complementary Metal Oxide Semiconductor Logic: A High Speed Differential Circuit

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CMOS (Complementary Metal Oxide Semiconductor) technology is in widespread use. However, a problem with CMOS logic circuits is low speed of operation, especially compared to competing (but less technically desirable) technologies such as Emitter Coupled Logic. Speed of operation can be increased if the effect of capacitances is minimized. In Phase I the principal investigator investigated capacitance minimization by operating CMOS logic circuits with voltage swings as small as reliability considerations (noise) will permit. He found a design technique which limits noise generated by the logic circuit itself. The objective of Phase II is to validate experimentally an innovative logic circuit capable of operating several fold faster than conventional circuits. He will layout, simulate, fabricate prototype chips, and measure the performance of a conventional (Manchester) 16-bit adder and a novel CMOS Avalanche CMOS 16-bit adder. Worst case propagation delay, cycle time and power dissipation will be measured. It is anticipated that the Avalanche adder will be four times faster than the conventional one. This proposal received high ratings on all SBIR Phase II evaluation points, which are as follows. 1. Phase I objectives were met completely with excellent results. 2. This design technique has technical importance and is likely to be applicable to a variety of CMOS circuit designs. 3. Phase II objectives are appropriate and attainable. 4. Scientific and engineering quality is high. 5. The principal investigator is highly qualified to do the work, and he has made important contributions in the past. 6. The budget is commensurate with thorough Phase II investigation. Successful research by the principal investigator will result in high likelihood of a desirable product, a significantly faster CMOS adder, as well as a practical design technique for CMOS circuits.