Avalanche Complementary Metal Oxide Semiconductor Logic: A High Speed Differential Circuit

雪崩互补金属氧化物半导体逻辑：高速差分电路

• 批准号: 8721764
• 负责人: Constantin Timoc
• 金额: $ 19.93万
• 依托单位: Spaceborne Inc
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1988
• 资助国家: 美国
• 起止时间: 1988-06-01 至 1991-11-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=8721764&HistoricalAwards=false
• 关键词: Avalanche; Complementary; Metal; Oxide; Semiconductor

CMOS (Complementary Metal Oxide Semiconductor) technology is in widespread use. However, a problem with CMOS logic circuits is low speed of operation, especially compared to competing (but less technically desirable) technologies such as Emitter Coupled Logic. Speed of operation can be increased if the effect of capacitances is minimized. In Phase I the principal investigator investigated capacitance minimization by operating CMOS logic circuits with voltage swings as small as reliability considerations (noise) will permit. He found a design technique which limits noise generated by the logic circuit itself. The objective of Phase II is to validate experimentally an innovative logic circuit capable of operating several fold faster than conventional circuits. He will layout, simulate, fabricate prototype chips, and measure the performance of a conventional (Manchester) 16-bit adder and a novel CMOS Avalanche CMOS 16-bit adder. Worst case propagation delay, cycle time and power dissipation will be measured. It is anticipated that the Avalanche adder will be four times faster than the conventional one. This proposal received high ratings on all SBIR Phase II evaluation points, which are as follows. 1. Phase I objectives were met completely with excellent results. 2. This design technique has technical importance and is likely to be applicable to a variety of CMOS circuit designs. 3. Phase II objectives are appropriate and attainable. 4. Scientific and engineering quality is high. 5. The principal investigator is highly qualified to do the work, and he has made important contributions in the past. 6. The budget is commensurate with thorough Phase II investigation. Successful research by the principal investigator will result in high likelihood of a desirable product, a significantly faster CMOS adder, as well as a practical design technique for CMOS circuits.

CMOS（互补金属氧化物半导体）技术是在 广泛使用。 然而，CMOS逻辑电路的问题是 操作速度，特别是与竞争对手相比（但更少） 技术上需要的）技术，例如ESCDMA耦合逻辑。 如果电容的影响被消除，则可以增加操作速度。 最小化 在第一阶段，主要研究者调查了 用电压操作CMOS逻辑电路的电容最小化方法 在可靠性考虑（噪声）允许的情况下，摆动尽可能小。 他 我发现了一种设计技术，可以限制逻辑电路产生的噪声 电路本身。 第二阶段的目标是验证 实验上，一种创新的逻辑电路能够操作几个 折叠速度比传统电路快。 他会设计，模拟， 制造原型芯片，并测量一个 传统的（曼彻斯特）16位加法器和一种新颖的CMOS雪崩CMOS 16-位加法器 最坏情况下的传播延迟、周期时间和功率 将测量耗散。 预计雪崩 加法器将比传统加法器快四倍。 该提案在所有SBIR第二阶段评估中获得了很高的评价 要点如下。 1. 第一阶段目标完全实现，表现出色 结果 2. 这种设计技术具有技术重要性， 以适用于各种CMOS电路设计。 3. 第二阶段的目标是适当的和可以实现的。 4. 科学和工程素质高。 5. 首席研究员非常有资格做 他的工作，并在过去作出了重要贡献。 6. 预算与整个第二阶段相称 调查 首席研究员的成功研究将导致高 一个理想的产品，一个明显更快的CMOS加法器， 以及CMOS电路的实用设计技术。