The Design of Secondary Caches

二级缓存的设计

• 批准号: 8902536
• 负责人: Mark Hill
• 金额: $ 5.55万
• 依托单位: University of Wisconsin-Madison
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1989
• 资助国家: 美国
• 起止时间: 1989-07-15 至 1991-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=8902536&HistoricalAwards=false
• 关键词: Design; Secondary; Caches

Cache hierarchies, heretofore rarely used, will become common in future shared-memory computers because: (1) processors are speeding up relative to main memories, (2) on-chip caches are useful but not large enough to obviate the need for off-chip caches and (3) specializing caches to reduce interconnection bandwidth is important to shared- memory multiprocessors. Secondary caches, those caches not adjacent to processors, need to be studied since they operate in a different system context than level one caches (those adjacent to processors). Few studies have examined secondary caches. Secondary caches, for example, need only do block transfers and are not referenced on every cycle as do level one caches. These and other differences between the operational requirements of secondary and level one caches should lead to significantly different implementations. Several aspects of secondary cache organization are examined including: (1) new methods for implementing set-associativity, (2) how cache coherency invalidates affect optional cache organization, and (3) when tag or data memory should be implemented with dynamic RAM. The methods used are analytic modeling, trace-driven simulation and trial implementations.

到目前为止很少使用的高速缓存层次结构将在未来的共享存储器计算机中变得常见，因为：(1)处理器相对于主存储器正在加速，(2)片上高速缓存是有用的，但不足以消除对片外高速缓存的需要，以及(3)专用高速缓存以减少互连带宽对于共享存储器多处理器来说是重要的。需要研究二级高速缓存，即那些不与处理器相邻的高速缓存，因为它们在与一级高速缓存(与处理器相邻的高速缓存)不同的系统环境中运行。很少有研究考察二级缓存。例如，二级缓存只需要进行块传输，并且不像一级缓存那样在每个周期都被引用。二级缓存和一级缓存的操作要求之间的这些差异和其他差异应该会导致显著不同的实现。研究了二级高速缓存组织的几个方面，包括：(1)实现组关联性的新方法，(2)高速缓存一致性无效如何影响可选的高速缓存组织，以及(3)何时应该使用动态RAM来实现标签或数据存储器。所使用的方法是分析建模、跟踪驱动的模拟和试验实现。