SHF: Small:Energy-Optimized Memory Hierarchies

SHF：小型：能量优化的内存层次结构

• 批准号: 1218323
• 负责人: Mark Hill
• 金额: $ 40万
• 依托单位: University of Wisconsin-Madison
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-07-01 至 2015-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1218323&HistoricalAwards=false
• 关键词: SHF; Small; Energy; Optimized; Memory

The early 21st century finds power and energy as the central challenges to continued improvements in computer system performance and cost. From handheld mobile devices to the data centers that support them, computer architects must invent new energy-efficient techniques to facilitate future innovations in science, education, government and commerce. In current systems, the memory hierarchy-which stores and moves the data values used and produced by the computation-consumes more energy than the computation itself. For example, obtaining operands for a double-precision multiply-add can consume 1.7 to 200 times the operation's energy depending on where in the memory hierarchy the values are stored. Improving the energy-efficiency of memory hierarchies can not only enable advances in future computer systems, but also reduces the emission of greenhouse gases.This project seeks novel memory hierarchy designs that minimize power and energy, rather than the classical focus on reducing latency and/or bandwidth. These designs build on three key hypotheses: (1) cache memories can reduce energy more than either latency or bandwidth, (2) optimizing latency becomes less important when it can be tolerated, and (3) overlapping activity does not save power, but can save energy due to static power dissipation. Initial research directions include (1) a technique to reduce address translation energy using a hybrid virtual/physical cache that eliminates the need to access a highly-associative TLB on every memory access and (2) energy-efficient cache hierarchies that use data compression techniques to replace the high energy cost of misses with lower compression and decompression overheads. This research will also extend the widely-used open-source gem5 simulation infrastructure to more accurately model the power and energy of emerging memory hierarchies.

21 世纪初，电力和能源成为计算机系统性能和成本持续改进的核心挑战。从手持移动设备到支持它们的数据中心，计算机架构师必须发明新的节能技术，以促进科学、教育、政府和商业领域的未来创新。在当前系统中，存储和移动计算使用和产生的数据值的内存层次结构比计算本身消耗更多的能量。例如，获取双精度乘加操作数可能会消耗运算能量的 1.7 到 200 倍，具体取决于值在内存层次结构中的存储位置。提高内存层次结构的能源效率不仅可以促进未来计算机系统的进步，还可以减少温室气体的排放。该项目寻求新颖的内存层次结构设计，最大限度地减少功耗和能源，而不是传统的关注减少延迟和/或带宽。这些设计建立在三个关键假设之上：(1) 高速缓冲存储器可以比延迟或带宽减少更多的能量，(2) 当可以容忍延迟时，优化延迟变得不那么重要，(3) 重叠活动不会节省功耗，但可以由于静态功耗而节省能量。最初的研究方向包括（1）一种使用混合虚拟/物理高速缓存来减少地址转换能量的技术，该技术消除了在每次内存访问时访问高度关联的 TLB 的需要；（2）高能效的高速缓存层次结构，使用数据压缩技术以较低的压缩和解压缩开销来取代未命中的高能源成本。这项研究还将扩展广泛使用的开源 gem5 模拟基础设施，以更准确地模拟新兴内存层次结构的功率和能量。