SHF: Small:Energy-Optimized Memory Hierarchies

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The early 21st century finds power and energy as the central challenges to continued improvements in computer system performance and cost. From handheld mobile devices to the data centers that support them, computer architects must invent new energy-efficient techniques to facilitate future innovations in science, education, government and commerce. In current systems, the memory hierarchy-which stores and moves the data values used and produced by the computation-consumes more energy than the computation itself. For example, obtaining operands for a double-precision multiply-add can consume 1.7 to 200 times the operation's energy depending on where in the memory hierarchy the values are stored. Improving the energy-efficiency of memory hierarchies can not only enable advances in future computer systems, but also reduces the emission of greenhouse gases.This project seeks novel memory hierarchy designs that minimize power and energy, rather than the classical focus on reducing latency and/or bandwidth. These designs build on three key hypotheses: (1) cache memories can reduce energy more than either latency or bandwidth, (2) optimizing latency becomes less important when it can be tolerated, and (3) overlapping activity does not save power, but can save energy due to static power dissipation. Initial research directions include (1) a technique to reduce address translation energy using a hybrid virtual/physical cache that eliminates the need to access a highly-associative TLB on every memory access and (2) energy-efficient cache hierarchies that use data compression techniques to replace the high energy cost of misses with lower compression and decompression overheads. This research will also extend the widely-used open-source gem5 simulation infrastructure to more accurately model the power and energy of emerging memory hierarchies.