Exploiting the Critical Path in the Design and Performance Analysis of Modern Processors

利用现代处理器设计和性能分析中的关键路径

• 批准号: 0105721
• 负责人: Mark Hill
• 金额: $ 42.25万
• 依托单位: University of Wisconsin-Madison
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2001
• 资助国家: 美国
• 起止时间: 2001-07-01 至 2006-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0105721&HistoricalAwards=false
• 关键词: Exploiting; Critical; Path; Design; Performance

An undesired consequence of the growing parallelism of modern processors is that it is dramatically more difficult to separate the events that limit execution speed from the events whose latencies are tolerated. A method for focusing design effort is critical-path analysis. This research proposes to apply critical-path analysis at the micro-architectural level, with the goal of detecting and eliminating execution bottlenecks.This research will explore the potential of the critical path in four interrelated efforts: (1) Modeling the micro-architectural critical path. The main task is to define a model of the critical path, i.e., the set of events and dependences in a micro-execution that will be exposed in the dependence graph on which the critical pathwill be computed. (2) Efficient tracing of the critical path. This effort will develop an on-line algorithm that will use a last-arrival edge at each node to calculate the critical path in one pass in a simulator. (3) Hardware critical-path predictors. This research will explore the use of approximation methods in avoiding the analysis of the entire dependence graph. (4) Criticality-aware processor policies. This research willuse hardware critical-path predictors to focus hardware policies on events likely to be on the critical path.

现代处理器的并行性不断增长的一个不期望的结果是，将限制执行速度的事件与其延迟被容忍的事件分开是非常困难的。 集中设计工作的一种方法是关键路径分析。 本研究提出在微体系结构层次上应用关键路径分析，以检测和消除执行瓶颈为目标，从四个方面探索关键路径的潜力：（1）建立微体系结构关键路径的模型，主要任务是定义关键路径的模型，即：微执行中的一组事件和依赖关系，将在依赖关系图中显示，关键路径将在依赖关系图上计算。 (2)关键路径的有效跟踪。这项工作将开发一种在线算法，该算法将在每个节点处使用最后到达边缘来计算模拟器中一次通过的关键路径。(3)硬件关键路径预测器。 本研究将探讨近似方法的使用，以避免整个依赖图的分析。 (4)临界感知处理器策略。 这项研究将使用硬件关键路径预测器来关注硬件策略可能在关键路径上的事件。