Exploiting the Critical Path in the Design and Performance Analysis of Modern Processors

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An undesired consequence of the growing parallelism of modern processors is that it is dramatically more difficult to separate the events that limit execution speed from the events whose latencies are tolerated. A method for focusing design effort is critical-path analysis. This research proposes to apply critical-path analysis at the micro-architectural level, with the goal of detecting and eliminating execution bottlenecks.This research will explore the potential of the critical path in four interrelated efforts: (1) Modeling the micro-architectural critical path. The main task is to define a model of the critical path, i.e., the set of events and dependences in a micro-execution that will be exposed in the dependence graph on which the critical pathwill be computed. (2) Efficient tracing of the critical path. This effort will develop an on-line algorithm that will use a last-arrival edge at each node to calculate the critical path in one pass in a simulator. (3) Hardware critical-path predictors. This research will explore the use of approximation methods in avoiding the analysis of the entire dependence graph. (4) Criticality-aware processor policies. This research willuse hardware critical-path predictors to focus hardware policies on events likely to be on the critical path.