RIA: An Integrated Approach to High-Performance Network Technology

一种综合的方法，对合成的高带宽，低， 延迟互连网络是追求的重点是 系统体系结构、VLSI特性和 包装技术 单边交叉点交换的新设计 可以在通信端口之间提供多条路径的模块， 正在研究多芯片开关。 提出了一种体系结构解决方案 对于同时开关噪声问题， 传统上在电路设计和封装级别解决。 小说 通过使用并行的快速仲裁和调度的方案 总线控制器在各种消息流量下进行了分析 条件 另一种方法使用人工神经网络， 争用解决。 交换机成本、性能和 可靠性是在这些工作负载下对各种芯片尺寸的研究。 拓扑测试技术用于大幅度减少测试 时间 研究结果正被纳入一套 软件工具最近在UT奥斯汀开发的计算机辅助 网络设计。 最近的技术进步促使人们重新对 交叉杆为基础的设计在行业中，尽管要求O (N2)开关. 事实上，通过考虑当前的VLSI和封装， 技术，它可以表明，功耗，电流驱动 能力和引脚排列的限制很容易超过电路密度的要求 交换网络。 这项研究旨在为以下方面奠定基础： 128-1024端口交叉开关的成本效益设计， 每个通道1千兆比特的带宽，可以形成下一个 大规模并行机和交换网络的产生。

An integrated approach towards the synthesis of high-bandwidth, low- latency interconnection networks is pursued that focuses on the interdependence of system architecture, VLSI characteristics and packaging technology. New designs of one-sided crosspoint switching modules that can provide several paths between communicating ports in multichip switches are being studied. An architecture solution is posed for the simultaneous switching noise problem and that has been traditionally tackled at the circuit design and packing levels. Novel schemes for fast arbitration and scheduling through the use of parallel bus-controllers are analyzed under a variety of message traffic conditions. An alternative approach uses artificial neural networks for contention resolution. Trade-offs between switch cost, performance and reliability are studies under these workloads for various chip sizes. Topological testing techniques are used for drastic reduction of test time. The research findings are being incorporated into a set of software tools recently developed at UT Austin for the computer-aided design of networks. Recent technological advances have prompted a resurgence of interest in cross bar-based designs in the industry, despite the requirement of O (N2) switches. Indeed, by considering current VLSI and packaging technology, it can be shown that power dissipation, current driving abilities and pinout limitations easily outweigh circuit density demands of switching networks. This research aims to lay the foundations for the cost-effective design of 128-1024 port crossbars with a sustained bandwidth of 1 GBytes per channel, that can form the core of the next generation of massively parallel machines and switching networks.