RIA: An Integrated Approach to High-Performance Network Technology

RIA：高性能网络技术的集成方法

• 批准号: 9011787
• 负责人: Joydeep Ghosh
• 金额: $ 6万
• 依托单位: University of Texas at Austin
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1990
• 资助国家: 美国
• 起止时间: 1990-09-01 至 1992-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9011787&HistoricalAwards=false
• 关键词: RIA; Integrated; Approach; Performance; Network

An integrated approach towards the synthesis of high-bandwidth, low- latency interconnection networks is pursued that focuses on the interdependence of system architecture, VLSI characteristics and packaging technology. New designs of one-sided crosspoint switching modules that can provide several paths between communicating ports in multichip switches are being studied. An architecture solution is posed for the simultaneous switching noise problem and that has been traditionally tackled at the circuit design and packing levels. Novel schemes for fast arbitration and scheduling through the use of parallel bus-controllers are analyzed under a variety of message traffic conditions. An alternative approach uses artificial neural networks for contention resolution. Trade-offs between switch cost, performance and reliability are studies under these workloads for various chip sizes. Topological testing techniques are used for drastic reduction of test time. The research findings are being incorporated into a set of software tools recently developed at UT Austin for the computer-aided design of networks. Recent technological advances have prompted a resurgence of interest in cross bar-based designs in the industry, despite the requirement of O (N2) switches. Indeed, by considering current VLSI and packaging technology, it can be shown that power dissipation, current driving abilities and pinout limitations easily outweigh circuit density demands of switching networks. This research aims to lay the foundations for the cost-effective design of 128-1024 port crossbars with a sustained bandwidth of 1 GBytes per channel, that can form the core of the next generation of massively parallel machines and switching networks.

对高带宽，低延迟互连网络的综合方法是追求，重点是系统架构，VLSI特性和封装技术的相互依存关系。可以在多片交换机通信端口之间提供多条路径的单侧交叉点交换模块的新设计正在研究中。针对同时开关噪声问题，提出了一种体系结构的解决方案，该问题传统上是在电路设计和封装层面解决的。分析了在各种消息流量条件下，利用并行总线控制器实现快速仲裁和调度的新方案。另一种方法是使用人工神经网络来解决争用。在不同芯片尺寸的工作负载下，研究了开关成本、性能和可靠性之间的权衡。拓扑测试技术用于大幅减少测试时间。这些研究成果正被纳入德克萨斯大学奥斯汀分校最近开发的一套软件工具中，用于网络的计算机辅助设计。尽管对O （N2）开关的要求很高，但最近的技术进步促使业界对基于交叉棒的设计重新产生了兴趣。事实上，考虑到当前的VLSI和封装技术，可以看出功耗、电流驱动能力和引脚限制很容易超过交换网络对电路密度的要求。本研究旨在为每通道持续带宽为1gb的128-1024端口交叉条的经济高效设计奠定基础，这可以形成下一代大规模并行机和交换网络的核心。