Distribution of VLSI Design Software for Education and Research

CAD设计工具，在大学的研究项目中产生 匹兹堡正在发展和加强，以使他们 并将其分发给普通用户。 这些工具 旨在帮助研究人员和教育工作者研究综合 从VHDL的描述中， 具体工具包括 增强的是：1）“Vcomp”的一个子集的VHDL的编译器 语言，2）“Vsim”相应的模拟器，3）同伴 为X11编写的原理图编辑器，4）一个配套的网表到 原理图工具为X11写的，5）“VF 2 VHDL”一个反向翻译器 从网表到VHDL。 任务包括：1）生成文档 为编译器和模拟器提供教程、示例和 课堂助手; 2）增强模拟器，以提供图形 基于斯坦福大学IRSIM/Analyzer的波形显示软件包; 3)将旧的原理图工具从sunview转换为X11; 4）清理 用于将网表分发到X11的原理图工具; 5） 将网表更新为VHDL工具。 通过电子邮件提供技术支持 提供。 这项补助金是根据软件资本化计划。

CAD design tools, produced in research projects at the University of Pittsburgh are being developed and enhanced so as to bring them into a state for distribution to general users. These tools are designed to help researchers and educators investigate synthesis of VLSI systems from VHDL descriptions. Specific tools being enhanced are: 1) "Vcomp" a compiler for a subset of the VHDL language, 2) "Vsim" the corresponding simulator, 3) A companion schematic editor written for X11, 4) A companion netlist-to- schematic tool written for X11, 5) "VF2VHDL" a reverse translator from netlists to VHDL. Tasks include: 1) Generate documentation for the compiler and simulator with tutorials, examples, and classroom aides; 2) Enhance the simulator to provide a graphical waveform display package based on IRSIM/Analyzer from Stanford; 3) Convert the old schematic tool from sunview to X11; 4) Clean up for distribution the netlist to schematic tool for X11; 5) Update the netlist to VHDL tool. Technical support via email will be provided. This grant is made under the Software Capitalization Program.