Collaborative Research: DESC: Type I: Towards Reduce- and Reuse-based Design of VLSI Systems with Heterogeneous Integration

合作研究:DESC:类型 I:采用异构集成实现基于缩减和重用的 VLSI 系统设计

基本信息

  • 批准号:
    2324946
  • 负责人:
  • 金额:
    $ 20万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Standard Grant
  • 财政年份:
    2023
  • 资助国家:
    美国
  • 起止时间:
    2023-10-01 至 2026-09-30
  • 项目状态:
    未结题

项目摘要

All aspects of computing, spanning from small chips to large datacenters, bear a carbon footprint (CFP) price tag. Although the semiconductor industry has dedicated several decades to making chips smaller, faster, and more energy-efficient, the environmental impact has often been neglected. While technology scaling and electronic design automation (EDA) have facilitated designing energy-efficient very large-scale integrated (VLSI) systems that lower operational CFP, the overall environmental footprint has continued to grow, primarily due to carbon emissions from chip design and manufacturing processes. To ensure the sustainable use of modern computing, it is crucial to develop design techniques that not only meet power, performance, and area (PPA) targets but also consider the CFP. With today's trillion-transistor VLSI systems being designed by heterogeneously integrating a set of chiplets, each corresponding to a single die, onto a substrate to reduce costs, and new design methodologies to support these technologies being rolled out, now is an ideal time to help shape these methodologies to be more sustainable. The novelty of this project lies in paving a path toward sustainable design and manufacturing of VLSI systems through heterogeneous integration (HI). It defines metrics related to CFP and develops simulators and optimizers that integrate with design methodologies to measure and reduce the overall CFP. Inspired by the principles of environmental sustainability—reduce, reuse, and recycle—this project aims to decrease the CFP associated with modern heterogeneous VLSI systems. HI systems offer great potential for sustainable computing by "reducing" carbon emissions through minimized computation required for designing each component from scratch and by "reusing" pre-designed chiplet intellectual property (IP) blocks through hierarchical approaches. Reusing chiplets across multiple designs, implemented in different technology nodes, within the current generation of integrated circuits (ICs) and even in future generations can significantly alleviate the manufacturing CFP. This project develops EDA approaches that (a) measure the carbon impact of heterogeneous VLSI system by building simulators that analyze its CFP across the design, manufacturing, and operational levels of a supply chain; (b) design methods for building high-performance HI systems, a new capability to be developed (since viable HI design flows do not exist today), tuned for efficient computation to reduce design-time carbon; (c) extend methodologies in the design task to incorporate the simulators from the measure task, to optimize the carbon footprint of a design, subject to PPA specifications on the HI design. This project outlines environmentally conscious computing practices by emphasizing the integration of CFP-related metrics into HI design methodologies and brings the community's attention to this critical issue in the semiconductor industry.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
计算的各个方面,从小型芯片到大型计算机,都有碳足迹(CFP)的价格标签。虽然半导体行业已经花费了几十年的时间来制造更小,更快,更节能的芯片,但环境影响往往被忽视。虽然技术扩展和电子设计自动化(EDA)促进了设计节能的超大规模集成(VLSI)系统,降低了操作CFP,但总体环境足迹继续增长,主要是由于芯片设计和制造过程的碳排放。为了确保现代计算的可持续使用,开发不仅满足功耗、性能和面积(PPA)目标而且考虑CFP的设计技术至关重要。随着当今的万亿晶体管超大规模集成电路系统的设计,通过异构集成一组小芯片,每个对应于一个单一的芯片,到基板上,以降低成本,和新的设计方法,以支持这些技术正在推出,现在是一个理想的时间来帮助塑造这些方法更可持续。该项目的新奇在于通过异构集成(HI)为超大规模集成电路系统的可持续设计和制造铺平了道路。它定义了与CFP相关的指标,并开发了模拟器和优化器,这些模拟器和优化器与设计方法相结合,以测量和降低整体CFP。受环境可持续性原则的启发-减少、再利用和重复利用-该项目旨在减少与现代异构VLSI系统相关的CFP。HI系统通过从头开始设计每个组件所需的最小化计算来“减少”碳排放,并通过分层方法“重用”预先设计的小芯片知识产权(IP)块,从而为可持续计算提供了巨大的潜力。在当前一代集成电路(IC)内甚至在未来几代集成电路中,跨在不同技术节点中实现的多个设计重用小芯片可以显著减轻制造CFP。本项目开发EDA方法,(a)通过构建模拟器,分析供应链的设计、制造和运营层面的CFP,测量异构VLSI系统的碳影响;(B)构建高性能HI系统的设计方法,这是一种有待开发的新能力(因为目前不存在可行的HI设计流程),调整为有效计算以减少设计时碳;(c)扩展设计工作中的方法,以纳入测量工作中的模拟器,从而优化设计的碳足迹,但须符合关于HI设计的PPA规格。该项目通过强调将CFP相关指标整合到HI设计方法中,概述了具有环境意识的计算实践,并引起了社区对半导体行业这一关键问题的关注。该奖项反映了NSF的法定使命,并通过使用基金会的知识价值和更广泛的影响审查标准进行评估,被认为值得支持。

项目成果

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Sachin Sapatnekar其他文献

Sachin Sapatnekar的其他文献

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{{ truncateString('Sachin Sapatnekar', 18)}}的其他基金

Collaborative Research: SHF: Medium: Automated energy-efficient sensor data winnowing using native analog processing
协作研究:SHF:中:使用本机模拟处理进行自动节能传感器数据筛选
  • 批准号:
    2212345
  • 财政年份:
    2022
  • 资助金额:
    $ 20万
  • 项目类别:
    Continuing Grant
SHF: Small: Enchancing the Reliability of Mixed-Signal Integrated Circuits
SHF:小型:提高混合信号集成电路的可靠性
  • 批准号:
    1714805
  • 财政年份:
    2017
  • 资助金额:
    $ 20万
  • 项目类别:
    Standard Grant
SHF: Small: Collaborative Research:Variation-Resilient VLSI Systems with Cross-Layer Controlled Approximation
SHF:小型:协作研究:具有跨层控制逼近的抗变化 VLSI 系统
  • 批准号:
    1525925
  • 财政年份:
    2015
  • 资助金额:
    $ 20万
  • 项目类别:
    Standard Grant
SHF: Small: Stress Management in Integrated Circuits
SHF:小型:集成电路的压力管理
  • 批准号:
    1421606
  • 财政年份:
    2014
  • 资助金额:
    $ 20万
  • 项目类别:
    Standard Grant
SHF: Medium: Collaborative Research: AgELESS: Aging Estimation and Lifetime Enhancement in Silicon Systems
SHF:媒介:合作研究:AgELESS:硅系统中的老化估计和寿命增强
  • 批准号:
    1162267
  • 财政年份:
    2012
  • 资助金额:
    $ 20万
  • 项目类别:
    Continuing Grant
SHF: Small: Enabling Resiliency in Nanometer-Scale CMOS Circuits
SHF:小:实现纳米级 CMOS 电路的弹性
  • 批准号:
    1017778
  • 财政年份:
    2010
  • 资助金额:
    $ 20万
  • 项目类别:
    Standard Grant
An Integrated Design and CAD Approach for Efficient Power Delivery in Multicore Processors
用于实现多核处理器高效供电的集成设计和 CAD 方法
  • 批准号:
    0903427
  • 财政年份:
    2009
  • 资助金额:
    $ 20万
  • 项目类别:
    Standard Grant
Thermal Effects in Integrated Circuits
集成电路中的热效应
  • 批准号:
    0541367
  • 财政年份:
    2006
  • 资助金额:
    $ 20万
  • 项目类别:
    Continuing Grant
Stochastically-inspired methods for solving systems of linear equations
求解线性方程组的随机方法
  • 批准号:
    0634802
  • 财政年份:
    2006
  • 资助金额:
    $ 20万
  • 项目类别:
    Standard Grant
Design Automation Techniques for SOI and High-Performance Bulk CMOS Designs
SOI 和高性能 Bulk CMOS 设计的设计自动化技术
  • 批准号:
    0098117
  • 财政年份:
    2001
  • 资助金额:
    $ 20万
  • 项目类别:
    Standard Grant

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相似海外基金

Collaborative Research: Conference: DESC: Type III: Eco Edge - Advancing Sustainable Machine Learning at the Edge
协作研究:会议:DESC:类型 III:生态边缘 - 推进边缘的可持续机器学习
  • 批准号:
    2342498
  • 财政年份:
    2024
  • 资助金额:
    $ 20万
  • 项目类别:
    Standard Grant
Collaborative Research: Conference: DESC: Type III: Eco Edge - Advancing Sustainable Machine Learning at the Edge
协作研究:会议:DESC:类型 III:生态边缘 - 推进边缘的可持续机器学习
  • 批准号:
    2342497
  • 财政年份:
    2024
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    $ 20万
  • 项目类别:
    Standard Grant
Collaborative Research: DESC: Type I: FLEX: Building Future-proof Learning-Enabled Cyber-Physical Systems with Cross-Layer Extensible and Adaptive Design
合作研究:DESC:类型 I:FLEX:通过跨层可扩展和自适应设计构建面向未来的、支持学习的网络物理系统
  • 批准号:
    2324936
  • 财政年份:
    2024
  • 资助金额:
    $ 20万
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合作研究:DESC:类型 I:FLEX:通过跨层可扩展和自适应设计构建面向未来的、支持学习的网络物理系统
  • 批准号:
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  • 财政年份:
    2024
  • 资助金额:
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Collaborative Research: DESC: Type II: REFRESH: Revisiting Expanding FPGA Real-estate for Environmentally Sustainability Heterogeneous-Systems
合作研究:DESC:类型 II:REFRESH:重新审视扩展 FPGA 空间以实现环境可持续性异构系统
  • 批准号:
    2324865
  • 财政年份:
    2023
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合作研究:DESC:类型 1:用于可持续计算的软硬件回收和修复数据集基础设施 (SHReDI)
  • 批准号:
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Collaborative Research: DESC: Type I: A User-Interactive Approach to Water Management for Sustainable Data Centers: From Water Efficiency to Self-Sufficiency
合作研究:DESC:类型 I:可持续数据中心水资源管理的用户交互方法:从用水效率到自给自足
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合作研究:DESC:类型 2:Delphi:可持续边缘设备的生命周期感知设计框架
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