RIA: New Approaches to Partitioning for Large-Scale VLSI Systems

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The research is on high-level system design, with a focus on partitioning logic among functional modules. Three new problem formulations and algorithms for performance driven layout are being investigated. These are: (1) numerical methods for finding sparse cuts for logic bi-partitioning with extensions to multi-way logic partitions; (2) techniques for estimating rapidly optimal solution values in large scale partition problems. These methods are based on random walks and the theory of simulated annealing, and have extensions to module area estimation for floorplan synthesis; and (3) a theoretical foundation (weighted module packing) for the performance-driven partitioning problem. Provably good algorithms for this problem are being examined.