SHF: Small: Research on Architecture-Level Estimation and Optimization for Networks-On-Chip Building Blocks

SHF：小型：片上网络构建模块的架构级估计和优化研究

• 批准号: 1116667
• 负责人: Andrew Kahng
• 金额: $ 45万
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-09-01 至 2015-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1116667&HistoricalAwards=false
• 关键词: SHF; Small; Research; Architecture; Level

Networks-on-chip (NoCs) are an on-chip interconnection fabric of choice for general-purpose chip multiprocessors and application-specific multiprocessor systems-on-chip. This project focuses on network-on-chip modeling and optimization to enable early-stage design exploration that fully elaborates the achievable envelope of NoC power, area, speed, reliability and cost. An architectural estimation thrust develops new architecture-level estimation methods that are portable to different router microarchitectures and that can accurately capture implementation effects. The thrust addresses the automatic generation of architectural estimation models, the modeling of chip design implementation flow choices and their impacts, and new trace-aware and workload-dependent estimations. An architectural optimization thrust develops new methodologies for trace-driven optimization of router configurations, packet routing and network topology, with consideration of runtime network resource contentions. Successful completion of this project will help network-on-chip and multiprocessor system-on-chip designers reduce design effort while improving chip area, delay and power metrics. This will be enabling to the efficient design of more complex, higher-functionality integrated-circuit products within given cost and power limits. The research will also produce software tools to establish a foundation for further work by other research groups. Through research participation, both graduate and undergraduate students will be trained in this emerging aspect of system-on-chip design.

片上网络（Networks-on-Chip，NoC）是通用片上多处理器和专用片上多处理器系统的片上互连结构的选择。该项目专注于片上网络建模和优化，以实现早期设计探索，充分阐述NoC功率，面积，速度，可靠性和成本的可实现范围。 一个架构的估计推力开发新的架构级的估计方法，可移植到不同的路由器微架构，可以准确地捕捉实施效果。 推力解决自动生成的架构估计模型，芯片设计实现流程的选择和它们的影响建模，和新的跟踪感知和工作负载相关的估计。 一个架构优化推力发展的跟踪驱动的路由器配置，数据包路由和网络拓扑结构的优化，考虑运行时的网络资源竞争的新方法。该项目的成功完成将有助于片上网络和多处理器片上系统设计人员减少设计工作，同时改善芯片面积，延迟和功耗指标。这将使更复杂，更高功能的集成电路产品的有效设计在给定的成本和功率限制。这项研究还将产生软件工具，为其他研究小组的进一步工作奠定基础。 通过参与研究，研究生和本科生将在片上系统设计的这一新兴方面接受培训。