SHF: Medium: Collaborative Research: 3D Integration of Heterogeneous Dies

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The dramatic improvements in electronic devices in the last 40 years have substantially drawn on Moore's law which predicts a steady increase in transistor density in semiconductor chips, with implied improvements in cost and power. But Moore's law is now slowing, while cost improvements now rely on very large production volumes to justify billion-dollar in investments in manufacturing infrastructure. Among alternative chip design methodologies, three-dimensional chip design currently shows significant momentum and promise for commercial products. Three-dimensional chips can be produced by vertical stacking of conventional two-dimensional chips and connecting them with through-silicon vias. Despite a number of unsolved technical problems, such three-dimensional chips reduce the form-factor and interconnect, while improving yield. This research explores heterogeneous 3D chip design seeking the flexibility to combine different types of two-dimensional chips (different types of memories, fast logic, low-power logic, FPGAs, analog circuits, micro- and nano-electromechanical components, etc.), which cannot be reliably manufactured on a single conventional die. This research will reduce cost of 3D designs and make them more practical by exploiting heterogeneity in all its aspects: (1) from dies fabricated in different process nodes to interconnects realized with TSVs, silicon interposers and wire bonds; (2) from system performance (macro blocks with different frequency requirements) to system activity (blocks that are standby-dominant vs. actively-switching); and (3) at the physical design level, from criticality (performance slack) to connectivity (bisection bandwidths or netcuts) across the physical hierarchy from block-level down to gate-level. Our research scope spans three main axes -- 3D IC implementation architectures, technology and design aspects of heterogeneity, and algorithmic optimizations. Being able to combine heterogeneous semiconductor dies in a working electronic system promises significant competitive advantage in price, performance and functionality. Such ability facilitates new types of electronic products, with clear benefits to design and manufacturing companies, as well as to the society. An example application here is a cellular phone, which integrated several micro-processors, analog circuit components and antennas, signal-processing units, accelerometers etc. Being able to revise one of these blocks without altering the supply chain for other blocks reduces the risk and cost of improvements to successful designs. Students will be trained to contribute to the design and revision of such designs, and to perform further research on alternative chip design techniques.