SHF: Medium: Collaborative Research: 3D Integration of Heterogeneous Dies

SHF：媒介：协作研究：异质模具的 3D 集成

• 批准号: 1162085
• 负责人: Andrew Kahng
• 金额: $ 24.35万
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-07-01 至 2016-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1162085&HistoricalAwards=false
• 关键词: SHF; Medium; Collaborative; Research; 3D

The dramatic improvements in electronic devices in the last 40 years have substantially drawn on Moore's law which predicts a steady increase in transistor density in semiconductor chips, with implied improvements in cost and power. But Moore's law is now slowing, while cost improvements now rely on very large production volumes to justify billion-dollar in investments in manufacturing infrastructure. Among alternative chip design methodologies, three-dimensional chip design currently shows significant momentum and promise for commercial products. Three-dimensional chips can be produced by vertical stacking of conventional two-dimensional chips and connecting them with through-silicon vias. Despite a number of unsolved technical problems, such three-dimensional chips reduce the form-factor and interconnect, while improving yield. This research explores heterogeneous 3D chip design seeking the flexibility to combine different types of two-dimensional chips (different types of memories, fast logic, low-power logic, FPGAs, analog circuits, micro- and nano-electromechanical components, etc.), which cannot be reliably manufactured on a single conventional die. This research will reduce cost of 3D designs and make them more practical by exploiting heterogeneity in all its aspects: (1) from dies fabricated in different process nodes to interconnects realized with TSVs, silicon interposers and wire bonds; (2) from system performance (macro blocks with different frequency requirements) to system activity (blocks that are standby-dominant vs. actively-switching); and (3) at the physical design level, from criticality (performance slack) to connectivity (bisection bandwidths or netcuts) across the physical hierarchy from block-level down to gate-level. Our research scope spans three main axes -- 3D IC implementation architectures, technology and design aspects of heterogeneity, and algorithmic optimizations. Being able to combine heterogeneous semiconductor dies in a working electronic system promises significant competitive advantage in price, performance and functionality. Such ability facilitates new types of electronic products, with clear benefits to design and manufacturing companies, as well as to the society. An example application here is a cellular phone, which integrated several micro-processors, analog circuit components and antennas, signal-processing units, accelerometers etc. Being able to revise one of these blocks without altering the supply chain for other blocks reduces the risk and cost of improvements to successful designs. Students will be trained to contribute to the design and revision of such designs, and to perform further research on alternative chip design techniques.

在过去的40年里，电子设备的戏剧性改进在很大程度上借鉴了摩尔定律，该定律预测半导体芯片中的晶体管密度将稳步增加，同时在成本和功率方面也有所改善。但摩尔定律现在正在放缓，而成本的改善现在依赖于非常大的生产量，以证明在制造业基础设施上投资数十亿美元是合理的。在可供选择的芯片设计方法中，三维芯片设计目前显示出巨大的商业化势头和前景。三维芯片可以通过将传统的二维芯片垂直堆叠并通过硅通孔连接来制造。尽管存在许多尚未解决的技术问题，但这种三维芯片在降低外形系数和互连程度的同时，还提高了产量。这项研究探索了不同类型的3D芯片设计，寻求将不同类型的二维芯片(不同类型的存储器、快速逻辑、低功率逻辑、现场可编程门阵列、模拟电路、微型和纳米机电元件等)组合在一起的灵活性，这些芯片不能在单个传统模具上可靠地制造。这项研究将通过利用各个方面的异构性来降低3D设计的成本并使其更加实用：(1)从在不同工艺节点制造的芯片到使用TSV、硅插入器和引线键合实现的互连；(2)从系统性能(具有不同频率要求的宏块)到系统活动(备用主导与主动切换的块)；以及(3)在物理设计级别，从关键程度(性能松弛)到跨物理层级从块级向下到门级的连接(平分带宽或网切)。我们的研究范围跨越三个主要轴线--3DIC实现体系结构、异构性的技术和设计方面以及算法优化。能够在一个工作的电子系统中组合异质半导体芯片，有望在价格、性能和功能上获得显著的竞争优势。这种能力促进了新型电子产品的开发，对设计和制造公司以及社会都有明显的好处。这里的一个示例应用是蜂窝电话，它集成了几个微处理器、模拟电路组件和天线、信号处理单元、加速计等。能够修改其中一个模块而不改变其他模块的供应链，降低了改进成功设计的风险和成本。学生将接受培训，为此类设计的设计和修改做出贡献，并对替代芯片设计技术进行进一步研究。