Integrated Framework for Test Synthesis, Power Optimization, and Reliable Design of VLSI Circuits

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This research is an integrated approach to design of VLSI circuits, with an emphasis on developing tests for thermal and electrical stress, and power management. The first goal is to use stress testing as a low-cost alternative to burn-in. Methods to synthesize tests for electrical and thermal stress based on accurate measure of signal activity are being explored. In low power design, the following are being pursued: 1. develop Monte Carlo based approaches estimation of signal and glitching activity in sequential and DSP circuits; 2. find architectural and system-level power minimization techniques; 3. investigate current switching techniques for power management; and 4. design layout algorithms for circuits with low power consumption. Sample sequential and digital signal processing circuits are being synthesized.