Sub-Threshold Digital Logic

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Ultra low power digital logic design can be achieved by operating transistors in the sub-threshold region. The device mimics and ideal constant current source for almost the whole VDS range. For serially connected transistors, the VDS drop on each transistor is negligible, which allows the implementation of large complex gates. The design in the sub-threshold region can be subdivided into device and circuit issues. At the device level, scaling issues are being investigated. At the circuit level, robustness, performance-power trade-offs and the applicability of circuit design based on various logic families (e.g. CMOS, Pseudo-NMOS, Source Coupled Logic, and Differential Current Switch Logic) are being studied. Several logic families are being designed to work specifically in the sub-threshold region. Comparisons with other low power design techniques, e.g. adiabatic Quasii-Static CMOS logic, are being made. Methods for noise analysis, including flicker and thermal noised, are being explored.