A Framework for Non-Silicon Based Nano-scale Design: From Devices to System Architecture

非硅纳米级设计框架：从器件到系统架构

• 批准号: 0702612
• 负责人: Kaushik Roy
• 金额: $ 36.13万
• 依托单位: Purdue University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-10-01 至 2011-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0702612&HistoricalAwards=false
• 关键词: Framework; Non; Silicon; Based; Nano

PROPOSAL NO: 0702612INSTITUTION: Purdue UniversityPRINCIPAL INVESTIGATOR: Roy, KaushikTITLE: A Framework for Non-Silicon Based Nano-scale Design: From Devices to System ArchitectureABSTRACTThe progress towards the scaling limits of silicon-based semiconductor technology has raised interest in non-silicon nano-devices such as carbon nano-tube field effect transistors (CNFETs). CNFETs offer tremendous opportunity due to high integration, but to successfully exploit them, designers must overcome the challenges of high variation in device parameters, high defect rates (opens or shorts) and high power density expected in CNFET based designs. Unfortunately, the device/circuit and architecture models and simulation tools that could facilitate the development and validation of circuits and architectures to overcome these challenges do not exist. The PI proposes to (a) develop an integrated device/circuit/architecture models and simulation software to enable designers to evaluate the performance, power and yield of nano-scale designs and (b) evaluate the benefits of several circuit and architecture innovations that address the key challenges (process variation, defects and power) of nano-scale design.The tools and models developed as a part of this research will be made available to the research community through the Nanohub, developed at Purdue (http://www.nanohub.purdue.edu), which provides web-based access to computational tools and currently contains an array of simulation packages for semiconductor and molecular electronics. The availability of models will spur circuit and architecture innovations in the research community. The PI will develop new nano-electronic courses that will take an integrated approach to design. The courses will be based on the research findings and will be available for use. Participation of undergraduates, minorities and women will be actively encouraged through existing outreach platforms at Purdue such as LSAMP, Indiana as well as partnerships with other universities.

提案编号：0702612INSTUTION：普渡大学PRINCIPAL研究员：Roy，KaushikTITLE：A Frame for Non-Silicon Based Nano-Scale Design：From Devices to System Architecture(从器件到系统架构)简介硅基半导体技术在尺寸限制方面的进展引起了人们对诸如碳纳米管场效应晶体管(CNFET)等非硅纳米器件的兴趣。由于高集成度，CNFET提供了巨大的机会，但为了成功地开发这些机会，设计人员必须克服基于CNFET的设计所面临的器件参数高变化、高缺陷率(开路或短路)和高功率密度的挑战。遗憾的是，可以促进电路和体系结构的开发和验证以克服这些挑战的设备/电路和体系结构模型和仿真工具并不存在。PI建议(A)开发一个集成的器件/电路/架构模型和仿真软件，使设计者能够评估纳米级设计的性能、功率和成品率，以及(B)评估几种电路和架构创新的好处，这些创新解决了纳米级设计的关键挑战(工艺变化、缺陷和功率)。作为这项研究的一部分，开发的工具和模型将通过普渡大学(http://www.nanohub.purdue.edu)，)开发的NanoHub提供给研究界。NanoHub提供对计算工具的基于网络的访问，目前包含一系列用于半导体和分子电子学的仿真软件包。模型的可获得性将刺激研究界的电路和架构创新。PI将开发新的纳米电子课程，采用综合方法进行设计。这些课程将以研究结果为基础，并可供使用。将通过普渡大学现有的外展平台，如印第安纳州的LSAMP，以及与其他大学的伙伴关系，积极鼓励本科生、少数族裔和妇女的参与。