A Framework for Non-Silicon Based Nano-scale Design: From Devices to System Architecture

提案号：0702612机构：普度大学主要研究者：Roy， kaushik标题：非硅基纳米级设计框架：从器件到系统架构摘要硅基半导体技术的缩放限制的进展引起了人们对非硅纳米器件如碳纳米管场效应晶体管（cnfet）的兴趣。由于高集成度，CNFET提供了巨大的机会，但为了成功地利用它们，设计人员必须克服器件参数的高变化，高缺品率（开路或短路）和基于CNFET的设计中预期的高功率密度的挑战。不幸的是，可以促进电路和架构的开发和验证以克服这些挑战的器件/电路和架构模型和仿真工具并不存在。PI建议(a)开发集成器件/电路/体系结构模型和仿真软件，使设计人员能够评估纳米级设计的性能、功率和产量；(b)评估几种电路和体系结构创新的好处，这些创新解决了纳米级设计的关键挑战（工艺变化、缺陷和功率）。作为这项研究的一部分，开发的工具和模型将通过普渡大学开发的Nanohub （http://www.nanohub.purdue.edu）提供给研究界，该中心提供基于网络的计算工具访问，目前包含一系列半导体和分子电子学的模拟软件包。模型的可用性将刺激研究界的电路和架构创新。PI将开发新的纳米电子课程，这些课程将采用综合方法进行设计。这些课程将以研究结果为基础，并可供使用。普渡大学将通过印第安纳州LSAMP等现有的外展平台，以及与其他大学的合作伙伴关系，积极鼓励本科生、少数族裔和女性的参与。

PROPOSAL NO: 0702612INSTITUTION: Purdue UniversityPRINCIPAL INVESTIGATOR: Roy, KaushikTITLE: A Framework for Non-Silicon Based Nano-scale Design: From Devices to System ArchitectureABSTRACTThe progress towards the scaling limits of silicon-based semiconductor technology has raised interest in non-silicon nano-devices such as carbon nano-tube field effect transistors (CNFETs). CNFETs offer tremendous opportunity due to high integration, but to successfully exploit them, designers must overcome the challenges of high variation in device parameters, high defect rates (opens or shorts) and high power density expected in CNFET based designs. Unfortunately, the device/circuit and architecture models and simulation tools that could facilitate the development and validation of circuits and architectures to overcome these challenges do not exist. The PI proposes to (a) develop an integrated device/circuit/architecture models and simulation software to enable designers to evaluate the performance, power and yield of nano-scale designs and (b) evaluate the benefits of several circuit and architecture innovations that address the key challenges (process variation, defects and power) of nano-scale design.The tools and models developed as a part of this research will be made available to the research community through the Nanohub, developed at Purdue (http://www.nanohub.purdue.edu), which provides web-based access to computational tools and currently contains an array of simulation packages for semiconductor and molecular electronics. The availability of models will spur circuit and architecture innovations in the research community. The PI will develop new nano-electronic courses that will take an integrated approach to design. The courses will be based on the research findings and will be available for use. Participation of undergraduates, minorities and women will be actively encouraged through existing outreach platforms at Purdue such as LSAMP, Indiana as well as partnerships with other universities.