SHF: Small: Ultra Low Power Neuromorphic Computing with Spin-devices

MOS（金属氧化物半导体）晶体管，作为开/关开关，已经成为开关函数和布尔逻辑抽象的理想匹配，它们（连同冯·诺伊曼结构）构成了现代计算的基础。虽然当前的计算平台非常适合涉及算术计算以及存储和检索大量数据的应用程序，但众所周知，它们在执行人类日常执行的任务（如视觉识别、语义分析和推理）时效率非常低——需要多几个数量级的能量消耗。提出的研究背后的关键见解是，新兴的基于自旋扭矩的器件使得以高能效的方式实现神经元功能成为可能，远远超出了CMOS（互补MOS）的能力。这是由于两个因素——这些设备的特性和神经元的功能之间的内在匹配（导致所需设备数量的急剧减少），以及超低电压操作（~20mV）的可能性。受到这一愿景的启发，pi（主要研究人员）提出了一个研究计划，涵盖从设备到架构的各个领域，以研究基于自旋的神经形态计算。拟议研究的目标是：(i)确定基于自旋的设备技术对神经形态计算的好处（其中CMOS实现能效低下），（ii）协同探索自旋设备，电路和架构，这些设备与CMOS集成以增强其能力，（iii）将拟议研究的结果纳入教育和推广计划。该项目将利用普渡大学的外展项目，包括NCN（计算纳米技术网络）的外展项目，以及工程学院的女性和少数族裔工程项目，让本科生和少数族裔学生参与拟议的研究。pi将开发一个夏季REU（本科生研究经验）项目，该项目建立在他们之前将本科生融入其研究小组的经验基础上。该项目的广泛性为本科生提供了一个有吸引力的机会，不仅可以探索新颖的研究，还可以接触到自旋电子学和神经形态计算的新兴领域。该项目还将与主要为本科生和少数族裔服务的机构建立研究、指导和教育伙伴关系。

MOS (metal-oxide-semiconductor) transistors, being on/off switches, have served as an ideal match to the abstractions of switching functions and Boolean logic, which (together with von Neumann architecture) form the underpinnings of modern computing. While current computing platforms are well-suited to applications that involve arithmetic computations and storing and retrieving large amounts of data, they are known to be highly inefficient - requiring orders of magnitude more energy consumption - for performing tasks that humans routinely perform, such as visual recognition, semantic analysis, and reasoning. The key insight behind the proposed research is that emerging spin torque based devices make it possible to realize the neuron functionality in a highly energy efficient manner, well beyond the capabilities of CMOS (complementary MOS). This is due to two factors - the inherent match between the characteristics of these devices and the functionality of a neuron (leading to a drastic decrease in the number of devices required), and the possibility of ultra-low voltage operation (~20mV). Inspired by this vision, the PIs (principal investigators) propose a research program that spans from devices to architectures to investigate spin-based neuromorphic computing. The goals of the proposed research are to (i) establish the benefits of spin-based device technologies for neuromorphic computing (where CMOS implementations are energy-inefficient), (ii) synergistically explore spin devices, circuits and architecture in a regime where these devices are integrated with CMOS to augment its capabilities and (iii) incorporate the findings from the proposed research in education and outreach programs. The project will leverage outreach programs at Purdue, including the outreach program at NCN (Network for Computational Nanotechnology), and the Women and Minority in Engineering programs in the College of Engineering, to involve undergraduates and minority students in the proposed research. The PIs will develop a summer REU (Research Experiences for Undergraduates) program that builds on their prior experience in integrating undergraduate students into their research groups. The broad nature of the proposed project provides an attractive opportunity for undergraduate students to not only explore novel research, but also get exposed to the emerging fields of spintronics and neuromorphic computing. The project will also establish research, mentoring and education partnerships with primarily undergraduate and minority serving institutions.