Mapping Time Oriented Tools for Logic Emulation

本研究的目标是为逻辑仿真开发快速的映射工具和体系结构，以大大减少映射时间，从而提高逻辑仿真的有用性和逻辑仿真的速度。正在开发的是：1)集成了分解和覆盖的技术映射工具，以及2)使用分区方法进行更高质量的全局布局的布局工具。这些设计旨在改善基于FPGA的实现的映射时间和结果质量。路由复杂性估计器也在开发中，以指导算法选择。它们在许多技术中利用了映射时间和质量之间的权衡。还在研究用于逻辑仿真器的新的FPGA体系结构，以及能够支持更快的映射时间但仍能获得高质量结果的系统。这些步骤被集成到一个完整的面向映射时间的工具套件中，用于逻辑仿真，该工具套件利用这些系统中的映射时间/质量权衡。

The goal of this research is to develop fast mapping tools and architectures for logic emulations that can greatly reduce the mapping time, and thus improve the usefulness of logic emulation, and the speed of logic simulation. Being developed are: 1) technology mapping tools that integrate decomposition and covering, and 2) placement tools that use partitioning methods to do higher- quality global placement. These are designed to improve both the mapping times and resulting quality for FPGA-based implementations. Routing complexity estimators are also being developed to guide algorithm choice. These exploit the mapping time-quality tradeoffs in many techniques. Also being investigated are new FPGA architectures for logic emulators, and systems that can support much faster mapping times, yet still achieve high quality results. These steps are being integrated into a complete mapping-time oriented tool suite for logic emulation which exploits the mapping time/quality tradeoff in these systems.