Mapping Time Oriented Tools for Logic Emulation

映射面向时间的逻辑仿真工具

• 批准号: 9616572
• 负责人: Majid Sarrafzadeh
• 金额: $ 13.9万
• 依托单位: Northwestern University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1997
• 资助国家: 美国
• 起止时间: 1997-07-15 至 2000-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9616572&HistoricalAwards=false
• 关键词: Mapping; Time; Oriented; Tools; Logic

The goal of this research is to develop fast mapping tools and architectures for logic emulations that can greatly reduce the mapping time, and thus improve the usefulness of logic emulation, and the speed of logic simulation. Being developed are: 1) technology mapping tools that integrate decomposition and covering, and 2) placement tools that use partitioning methods to do higher- quality global placement. These are designed to improve both the mapping times and resulting quality for FPGA-based implementations. Routing complexity estimators are also being developed to guide algorithm choice. These exploit the mapping time-quality tradeoffs in many techniques. Also being investigated are new FPGA architectures for logic emulators, and systems that can support much faster mapping times, yet still achieve high quality results. These steps are being integrated into a complete mapping-time oriented tool suite for logic emulation which exploits the mapping time/quality tradeoff in these systems.

本研究的目标是开发快速映射工具和逻辑仿真的架构，可以大大减少映射时间，从而提高逻辑仿真的有用性和逻辑仿真的速度。 正在制定的是：1）集成分解和覆盖的技术映射工具，2）使用分区方法进行更高质量全局布局的布局工具。 这些都是为了提高映射时间和基于FPGA的实现质量。 路由复杂性估计也正在开发，以指导算法的选择。 这些利用了许多技术中的映射时间-质量权衡。 还在研究用于逻辑仿真器的新FPGA架构，以及可以支持更快映射时间但仍能实现高质量结果的系统。 这些步骤被集成到一个完整的映射时间为导向的工具套件的逻辑仿真，利用这些系统中的映射时间/质量权衡。