Adaptive Reduced-Rank Interference Suppression: Algorithms, Performance, and Low Power VLSI

本研究涉及与降阶自适应滤波相关的算法、性能和硬件问题。降阶滤波器将输入的接收信号投影到较低维子空间，这与传统的满阶算法相比减少了所需的训练数据量。算法技术最初将在直接序列(DS)-码分多址(CDMA)干扰抑制的背景下进行研究，尽管它们可以应用于任何自适应线性滤波器。研究的重点是最近发展起来的一类基于Goldstein和Reed的多级Wiener滤波的降维自适应算法。该技术可以在很低的滤波阶的情况下实现满阶性能，从而实现快速收敛和跟踪。此外，这些算法不依赖于信号子空间的显式估计。该项目是多学科的，因为它结合了两个合作PI在自适应信号处理和低功耗VLSI设计领域的专业知识。研究的主要目标是构建一个低功耗专用硬件原型，该原型可以作为各种应用中的降阶滤波的计算引擎。要研究的算法问题包括滤波器阶的选择，在不同自适应滤波应用中的性能，如均衡，以及数值稳定性和动态范围问题。

This research is concerned with algorithmic, performance, and hardware issues related to reduced-rank adaptive filtering. Reduced-rank filters project the incoming received signal onto a lower dimensional subspace, which reduces the amount of training data needed relative to a conventional full-rank algorithm. Algorithmic techniques will be studied initially within the context of interference suppression for Direct Sequence (DS)-Code-Division Multiple Access (CDMA), although they can be applied to any adaptive linear filter. The focus of the research is on a recently developed class of reduced-rank adaptive algorithms based on the multi-stage Wiener filter of Goldstein and Reed. This technique can achieve full-rank performancewith a very low filter rank, which enables rapid convergence and tracking. Furthermore, these algorithmsdo not rely on an explicit estimate of the signal subspace. The project is multi-disciplinary in that it combines the expertise of the two co-PIs in the areas of adaptive signal processing and low power VLSI design.The main objective of the research is to build a low-power special purpose hardware prototype, which can serve as the computational engine for reduced-rank filtering in a variety of applications. Algorithmic issues to be studied include selection of filter rank, performance in different adaptive filtering applications, such as equalization, and numerical stability and dynamic range problems.