Adaptive Reduced-Rank Interference Suppression: Algorithms, Performance, and Low Power VLSI

自适应降阶干扰抑制：算法、性能和低功耗 VLSI

• 批准号: 0073686
• 负责人: Majid Sarrafzadeh
• 金额: $ 29.54万
• 依托单位: Northwestern University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-09-01 至 2004-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0073686&HistoricalAwards=false
• 关键词: Adaptive; Reduced; Rank; Interference; Suppression

This research is concerned with algorithmic, performance, and hardware issues related to reduced-rank adaptive filtering. Reduced-rank filters project the incoming received signal onto a lower dimensional subspace, which reduces the amount of training data needed relative to a conventional full-rank algorithm. Algorithmic techniques will be studied initially within the context of interference suppression for Direct Sequence (DS)-Code-Division Multiple Access (CDMA), although they can be applied to any adaptive linear filter. The focus of the research is on a recently developed class of reduced-rank adaptive algorithms based on the multi-stage Wiener filter of Goldstein and Reed. This technique can achieve full-rank performancewith a very low filter rank, which enables rapid convergence and tracking. Furthermore, these algorithmsdo not rely on an explicit estimate of the signal subspace. The project is multi-disciplinary in that it combines the expertise of the two co-PIs in the areas of adaptive signal processing and low power VLSI design.The main objective of the research is to build a low-power special purpose hardware prototype, which can serve as the computational engine for reduced-rank filtering in a variety of applications. Algorithmic issues to be studied include selection of filter rank, performance in different adaptive filtering applications, such as equalization, and numerical stability and dynamic range problems.

本研究主要针对降秩自适应滤波的演算法、效能与硬体问题。 降秩滤波器将输入的接收信号投影到较低维的子空间上，这相对于常规的满秩算法减少了所需的训练数据量。将首先在直接序列（DS）-码分多址（CDMA）的干扰抑制的背景下，虽然它们可以应用于任何自适应线性滤波器的干扰抑制技术进行研究。研究的重点是最近开发的一类基于Goldstein和Reed的多级维纳滤波器的降秩自适应算法。这种技术可以用很低的滤波器秩实现满秩性能，从而实现快速收敛和跟踪。 此外，这些算法不依赖于信号子空间的显式估计。该项目是多学科的，因为它结合了自适应信号处理和低功耗VLSI设计领域的专业知识，研究的主要目标是建立一个低功耗的专用硬件原型，它可以作为各种应用中的降秩滤波器的计算引擎。 要研究的数学问题包括滤波器秩的选择，在不同的自适应滤波应用中的性能，如均衡，以及数值稳定性和动态范围问题。