Algorithm Design for VLSI Layout

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This research is on algorithmic approaches to VLSI, and four problems are being investigated. These are: 1. Literal minimization in logic synthesis using an approach based on term intersection graphs. 2. Gate level placement problems using minimum floating Steiner trees. 3. Budget assignment in timing driven placement in which a novel optimization tool is being explored. 4. Clock tree design using a gated design which minimizes activity, hence power consumption. A coherent design system, incorporating above stages, is being developed.