Algorithm Design for VLSI Layout

VLSI布局算法设计

• 批准号: 9527389
• 负责人: Majid Sarrafzadeh
• 金额: $ 19.98万
• 依托单位: Northwestern University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1996
• 资助国家: 美国
• 起止时间: 1996-02-01 至 2000-01-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9527389&HistoricalAwards=false
• 关键词: Algorithm; Design; VLSI; Layout

This research is on algorithmic approaches to VLSI, and four problems are being investigated. These are: 1. Literal minimization in logic synthesis using an approach based on term intersection graphs. 2. Gate level placement problems using minimum floating Steiner trees. 3. Budget assignment in timing driven placement in which a novel optimization tool is being explored. 4. Clock tree design using a gated design which minimizes activity, hence power consumption. A coherent design system, incorporating above stages, is being developed.

这项研究是关于VLSI的算法方法，并研究了四个问题。它们是：1；基于项相交图的逻辑综合中的文字最小化方法。2. 使用最小浮动斯坦纳树的门级布置问题。3. 在时间驱动布局的预算分配中，一种新的优化工具正在被探索。4. 时钟树设计采用门控设计，最大限度地减少活动，从而减少功耗。目前正在制订一个包含上述各阶段的连贯的设计系统。