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Algorithm Design for VLSI Layout

Algorithm Design for VLSI Layout
VLSI布局算法设计
批准号:
9207267
负责人:
Majid Sarrafzadeh
金额:
$19.57万
依托单位:
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
1992
资助国家:
美国
项目状态:
已结题
起止时间:
1992-12-01 至 1996-11-30

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英文摘要
Sarrafzadeh The research is in four areas of geometric algorithms for design tools. The research topics are: 1. floor planning by graph dualization; 2. placement of modules by exploiting circuit regularities; 3. rectilinear Steiner tree problems; and 4. point dominance problems. In floor-planning, topological aspects of the problem are considered and geometric issues such as sizing are explored. A clustering technique for module placement, that exploits regularities in circuit structures, is being investigated. In this way natural clusters that reflect the hierarchical perspective of circuit connections can be built automatically. Problems in approximate designs for global and single layer routing using Steiner trees are being investigated. Point dominance, from computational geometry, is being applied to circuit layout problems.
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    2000
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