Innovation in VLSI Systems Education: Integration of High Level Synthesis, Analysis and Test Generation Research Results into Undergrad Minor Curriculum in VLSI Systems Engineering

Vemuri, Ranganadha Carter， Harold辛辛那提大学VLSI系统教育创新：将高级综合、分析和测试生成研究成果集成到VLSI系统工程本科辅修课程中CISE教育创新奖支持将高级VLSI综合、性能分析和测试向量生成研究集成到VLSI系统工程本科课程中。模型课程将包含以下主题：超大规模集成电路设计的高级功能和行为建模的开发、高级超大规模集成电路综合技术和工具的使用、在整个设计过程中开发和使用性能模型，以及设计验证测试的生成。课程支持材料将包括关于这些主题的迷你书、学期项目模块，以及最重要的，用于高级综合、性能分析和测试生成的免费软件工具。所有的课程材料都将通过互联网和万维网传播。

9634462 Vemuri, Ranganadha Carter, Harold University of Cincinnati Innovation in VLSI Systems Education: Integration of High Level Synthesis, Analysis and Test Generation Research Results into Undergraduate Minor Curriculum in VLSI Systems Engineering This CISE Educational Innovation award supports the integration of research in high-level VLSI synthesis, performance analysis and test vector generation into the undergraduate curriculum in VLSI systems engineering. The model curriculum will contain topics on the development of high-level functional and behavioral modeling of VLSI designs, use of high-level VLSI synthesis techniques and tools, developing and using performance models throughout the design process, and generation of design verification tests. Curriculum support material will include mini-books on these topics, term project modules, and, most importantly, free software tools for high-level synthesis, performance analysis and test generation. All of the curriculum material will disseminated through the Internet and the World-Wide-Web.