Noise-Shaping DACs for Delta-Sigma Data Converters

用于 Delta-Sigma 数据转换器的噪声整形 DAC

• 批准号: 9711331
• 负责人: Ian Galton
• 金额: $ 22.25万
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1997
• 资助国家: 美国
• 起止时间: 1997-07-01 至 2001-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9711331&HistoricalAwards=false
• 关键词: Noise; Shaping; DACs; Delta; Sigma

The unprecedented speed, integration density, and economy of modern CMOS circuit technology have fueled the rapid evolution of the computer industry, and hold the promise of similarly fueling the personal communications industry. However, the circuit technology tends to be highly optimized for digital circuits wherein precise analog performance is not critical. Since communication systems must transmit and receive analog waveforms, the most effective use of CMOS circuit technology for such applications requires on-chip analog-to-digital (A/D) and digital-to-analog (D/A) converters, and these are often the limiting factors in overall system price and performance. For low speed applications such as telephone modems, delta-sigma data converters have emerged as the method of choice for implementing the on-chip A/D and D/A converters because they are particularly amenable to high-precision CMOS implementation. The purpose of this research is to eliminate a major limitation suffered by existing delta-sigma data converters to facilitate their use in higher-speed applications such as personal wireless communication systems. Specifically, the research involves the development of practical multi-bit noise- shaping DACs to be used in delta-sigma data converters. These DACs avoid the severe component matching requirements of their conventional counterparts through a digital signal processing innovation that causes the noise arising from component mismatches to lie outside the signal band. Such DACs have the potential to significantly increase the present performance limits of delta-sigma data converters by eliminating the need for one-bit quantization. The primary goals of the research are to develop practical high-order noise-shaping DACs that extend the present performance limits of delta-sigma data converters, and to theoretically and experimentally quantify their performance.

现代CMOS电路技术前所未有的速度、集成密度和经济性推动了计算机行业的快速发展，并有望同样推动个人通信行业的发展。 然而，电路技术倾向于高度优化数字电路，其中精确的模拟性能并不重要。 由于通信系统必须发送和接收模拟波形，因此CMOS电路技术在此类应用中的最有效使用需要片上模数（A/D）和数模（D/A）转换器，而这些转换器通常是整个系统价格和性能的限制因素。 对于电话调制解调器等低速应用，Δ-Σ数据转换器已成为实现片上A/D和D/A转换器的首选方法，因为它们特别适合于高精度CMOS实现。 本研究的目的是消除现有的delta-sigma数据转换器所遭受的主要限制，以促进其在更高速度的应用，如个人无线通信系统中的使用。 具体而言，该研究涉及开发用于Δ-Σ数据转换器的实用多位噪声整形DAC。这些DAC通过数字信号处理创新避免了传统DAC的严格元件匹配要求，该创新使元件失配引起的噪声位于信号频带之外。 此类DAC无需1位量化，有可能显著提高Δ-Σ数据转换器的当前性能极限。 本研究的主要目标是开发实用的高阶噪声整形DAC，以扩展当前delta-sigma数据转换器的性能极限，并从理论和实验上量化其性能。