Noise-Shaping DACs for Delta-Sigma Data Converters

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The unprecedented speed, integration density, and economy of modern CMOS circuit technology have fueled the rapid evolution of the computer industry, and hold the promise of similarly fueling the personal communications industry. However, the circuit technology tends to be highly optimized for digital circuits wherein precise analog performance is not critical. Since communication systems must transmit and receive analog waveforms, the most effective use of CMOS circuit technology for such applications requires on-chip analog-to-digital (A/D) and digital-to-analog (D/A) converters, and these are often the limiting factors in overall system price and performance. For low speed applications such as telephone modems, delta-sigma data converters have emerged as the method of choice for implementing the on-chip A/D and D/A converters because they are particularly amenable to high-precision CMOS implementation. The purpose of this research is to eliminate a major limitation suffered by existing delta-sigma data converters to facilitate their use in higher-speed applications such as personal wireless communication systems. Specifically, the research involves the development of practical multi-bit noise- shaping DACs to be used in delta-sigma data converters. These DACs avoid the severe component matching requirements of their conventional counterparts through a digital signal processing innovation that causes the noise arising from component mismatches to lie outside the signal band. Such DACs have the potential to significantly increase the present performance limits of delta-sigma data converters by eliminating the need for one-bit quantization. The primary goals of the research are to develop practical high-order noise-shaping DACs that extend the present performance limits of delta-sigma data converters, and to theoretically and experimentally quantify their performance.