CIF: Small: Circumventing Present-Day Frequency Synthesis Limitations in Digital PLLs

用于频率合成的高性能锁相环(PLL)是几乎所有现代电子通信系统中的关键部件，通常是限制其性能的部件。尽管数字锁相环具有许多优势，但在当今高端频率合成应用中，如在4G移动系统中，数字锁相环并未取代模拟锁相环，远远达不到预期的5G要求。新一代移动通信系统将要求锁相环具有更高的精度、更低的功耗、更强的可重构性、更强的抗干扰性和更低的成本。为了实现这一目标，本项目将探索开发和设计数字锁相环的新技术。该项目的成功完成不仅将对通信行业产生强大的技术影响，还将通过培训他们加入劳动力队伍，为该行业培养下一代设计工程师。该项目的主要研究重点是理论，开发和优化使能新的信号处理技术及其严格的数学分析。此外，还将开发一种通过新技术实现的数字PLL原型IC，目标是实现同类最佳的5G射频频率合成性能。这项实验工作将提供指导理论工作的反馈，以及评估项目在实现其目标方面的成功程度的明确手段。

High-performance Phase Locked Loops (PLLs) for frequency synthesis are critical and are often performance-limiting components in nearly all modern electronic communication systems. Despite their many advantages, digital PLLs have not replaced analog PLLs in present-day high-end frequency synthesis applications such as in 4G mobile systems, and fall far short of anticipated 5G requirements. The new generation of mobile communication systems will require PLLs to have higher accuracy, lower power dissipation, greater re-configurability, greater immunity to interference, and lower costs. Towards this goal, this project will explore novel techniques for development and design of Digital PLLs. Successful completion of the project will not only have a strong technical impact on the communications industry, but will also educate the next generation of design engineers for the industry by training them to join the workforce.The primary research focus of this project is theoretical and is the development and optimization of enabling new signal processing techniques and their rigorous mathematical analyses. Additionally, a digital PLL prototype IC enabled by the new techniques will be developed that targets best-of-class 5G RF frequency synthesis performance. This experimental work will provide feedback that will guide the theoretical work as well as a definitive means of evaluating the success of the project in achieving its objective.