CIF: Small: Circumventing Present-Day Frequency Synthesis Limitations in Digital PLLs

CIF：小：规避当前数字 PLL 中的频率合成限制

• 批准号: 1617545
• 负责人: Ian Galton
• 金额: $ 45万
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2016
• 资助国家: 美国
• 起止时间: 2016-07-01 至 2020-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1617545&HistoricalAwards=false
• 关键词: CIF; Small; Circumventing; Present; Day

High-performance Phase Locked Loops (PLLs) for frequency synthesis are critical and are often performance-limiting components in nearly all modern electronic communication systems. Despite their many advantages, digital PLLs have not replaced analog PLLs in present-day high-end frequency synthesis applications such as in 4G mobile systems, and fall far short of anticipated 5G requirements. The new generation of mobile communication systems will require PLLs to have higher accuracy, lower power dissipation, greater re-configurability, greater immunity to interference, and lower costs. Towards this goal, this project will explore novel techniques for development and design of Digital PLLs. Successful completion of the project will not only have a strong technical impact on the communications industry, but will also educate the next generation of design engineers for the industry by training them to join the workforce.The primary research focus of this project is theoretical and is the development and optimization of enabling new signal processing techniques and their rigorous mathematical analyses. Additionally, a digital PLL prototype IC enabled by the new techniques will be developed that targets best-of-class 5G RF frequency synthesis performance. This experimental work will provide feedback that will guide the theoretical work as well as a definitive means of evaluating the success of the project in achieving its objective.

用于频率合成的高性能锁相环（PLL）是至关重要的，并且在几乎所有现代电子通信系统中通常是性能限制元件。尽管数字PLL具有许多优点，但在诸如4G移动的系统等当今高端频率合成应用中，数字PLL尚未取代模拟PLL，并且远远达不到预期的5G要求。新一代移动的通信系统将要求PLL具有更高的精度、更低的功耗、更大的可重构性、更强的抗干扰性以及更低的成本。为了达到这个目标，这个项目将探索数字PLL的开发和设计的新技术。该项目的成功完成不仅将对通信行业产生强大的技术影响，而且还将通过培训为行业培养下一代设计工程师。该项目的主要研究重点是理论，是开发和优化新的信号处理技术及其严格的数学分析。此外，还将开发一款采用新技术的数字PLL原型IC，以实现一流的5G RF频率合成性能。这项实验工作将提供反馈，指导理论工作，并作为评估项目是否成功实现其目标的明确手段。

项目成果

Spectral Breathing and Its Mitigation in Digital Fractional-N PLLs

数字小数 N PLL 中的频谱呼吸及其缓解

• DOI: 10.1109/jssc.2021.3074814
• 发表时间: 2021
• 期刊: IEEE Journal of Solid-State Circuits
• 影响因子: 5.4
• 作者: Alvarez-Fontecilla, Enrique;Helal, Eslam;Eissa, Amr I.;Galton, Ian
• 通讯作者: Galton, Ian