Digital Cancellation of Analog Mismatch Noise in Pipelined ADCs

这项研究的目的是通过开发一种能够校正模拟电路失配的数字信号处理技术来扩展流水线模数转换器(ADC)目前的性能限制。随着软件可重构和数字信号处理的最新趋势，流水线ADC已广泛应用于蜂窝电话基站和宽带有线调制解调器等应用中。然而，模拟元件失配将目前制造的流水线ADC实现的精度限制在低于许多通信应用所需的水平。例如，在目前转换率为10 MHz或以上的流水线ADC中，模拟元件失配造成的精度上限约为75dB峰值信噪比和失真(SINAD)。近年来，已经提出了几种不同的失配校准技术来解决失配问题，但到目前为止，它们还没有使突破上述75dBSINAD上限成为可能。问题是，迄今为止提出的校准技术最终受到其模拟组件的精度的限制，随着转换率的增加，模拟组件的精度往往会降低。这项研究涉及到一种新的流水线ADC失配校准技术的开发，以避免这一问题。新技术与其他失配校准方案的不同之处在于，它连续测量和消除ADC正常工作期间由于元件失配而产生的ADC输出中的噪声；在A/D转换之前不需要特殊的校准信号或自动校准阶段。完全使用数字逻辑来执行失配噪声的测量和消除，但与先前提出的数字校准技术不同，该技术不需要额外的流水线级或每个级的比特。研究的目标是1)改进工艺，2)通过模拟和理论分析来量化其性能极限，3)开发一种通过该技术实现创纪录性能的流水线ADC原型，作为原理证明。

The purpose of this research is to extend the present performance limits of pipelined analog-to-digital converters (ADCs) through the development of a digital signal processing technique that corrects for analog circuit mismatches. With recent trends toward software reconfigurability and digital signal processing, pipelined ADCs have become widely used in applications such as cellular telephone base-stations and wideband wireline modems. However, analog component mismatches have limited the accuracy achieved by present fabricated pipelined ADCs to levels below those desirable in many communications applications. For example, the accuracy ceiling imposed by analog component mismatches in present pipelined ADCs with conversion rates at or above 10MHz is approximately 75dB peak signal-to-noise-and-distortion (SINAD). Several distinct mismatch calibration techniques have been proposed in recent years to address the mismatch problem, but so far they have not made it possible to break through the above-mentioned 75dB SINAD ceiling. The problem is that the calibration techniques proposed to date are ultimately limited by the precision of their analog components, which tends to decrease as the conversion rate is increased. This research involves the development of a new pipelined ADC mismatch calibration technique that avoids this problem. The new technique differs from other mismatch calibration schemes in that it continuously measures and cancels noise in the ADC output arising from component mismatches during normal operation of the ADC; no special calibration signals or auto-calibration phase are required prior to A/D conversion. Both the measurement and cancellation of mismatch noise are performed entirely using digital logic, but unlike previously proposed digital calibration techniques the technique does not require additional pipeline stages or bits per stage. The objectives of the research are to 1) refine the technique, 2) quantify its performance limits through simulation and theoretical analyses, and 3) develop a CMOS pipelined ADC prototype that achieves record-setting performance enabled by the technique as a proof-of-principle.