CAREER: Interconnect-centric High-Level Synthesis in DSM Regime

职业：DSM 体系中以互连为中心的高级综合

• 批准号: 0093301
• 负责人: Srinivas Katkoori
• 金额: $ 31.12万
• 依托单位: University of South Florida
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2001
• 资助国家: 美国
• 起止时间: 2001-02-01 至 2006-01-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0093301&HistoricalAwards=false
• 关键词: CAREER; Interconnect; centric; Level; Synthesis

As the interconnect characteristics dominate in deep-sub-micron regime, we are developing an interconnect-centric high-level synthesis (HLS) framework in which delay, power, and routability, can be optimized. We are investigating two approaches: (1) Incremental approach: HLS is performed iteratively by taking into account net-level estimates obtained from a detailed floorplan and global route information; and (2) Composite Approach: HLS tasks (scheduling, allocation, and binding) as well as physical design tasks (placement and routing) are unified into one composite step. The novel features of the HLS framework are: (1) use of detailed interconnect timing models (moment-based, Elmore-delay based) in HLS flow; (2) routability driven HLS; and (3) usage of Rent's exponent as a routability metric. As part of education plan, we are: (1) developing a two course sequence (dual-level); (2) experimenting in VLSI education with the case-based (Harvard Business school) teaching style (popularly used the MBA field); (3) involving undergraduate minority students in VLSI EDA research; and (4) exposing K11-12 students to the field of VLSI chip design automation.

由于互连特性在深亚微米制度占主导地位，我们正在开发一个以互连为中心的高层次综合（HLS）框架，其中延迟，功率和可布线性，可以优化。我们正在研究两种方法：（1）增量方法：HLS通过考虑从详细的平面图和全局布线信息中获得的网络级估计来迭代执行;（2）复合方法：HLS任务（调度，分配和绑定）以及物理设计任务（布局和布线）被统一到一个复合步骤中。 HLS框架的新颖特征是：（1）在HLS流中使用详细的互连定时模型（基于时刻，基于Elmore延迟）;（2）可路由性驱动的HLS;以及（3）使用Rent指数作为可路由性度量。 作为教育计划的一部分，我们正在：（1）开发一个两个课程序列（双层次）;（2）在VLSI教育中尝试基于案例的教学风格（哈佛商学院）（流行于MBA领域）;（3）让本科少数民族学生参与VLSI EDA研究;以及（4）让K11-12学生接触VLSI芯片设计自动化领域。