Efficient and Performance Guaranteed Methods for Order Reduction and Analysis of VLSI Interconnect Circuits

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The advance of high-speed deep-submicron VLSI technology requires chipinterconnect and packaging to be modeled by distributed circuits. Such adetailed modeling level eventually results in large scale linear circuits tobe analyzed. Thus, the research objective is to develop new circuit orderreduction approach to evaluate the circuit performance and characteristicsin a reasonable time period and with a guaranteed performance, as requiredby real design practice.This project focuses on the following tasks:a) Develop new order reduction approaches that provide guaranteed performance;b) Derive correspondingly high efficiency numerical methods;c) Investigate the methods of maintaining preferred characteristics in thereduced order system as well as related implementation issues;d) Investigate wavelet method application in model order reduction andanalysis; ande) Contribute to graduate education at UT- Dallas and UNC-Charlotte.The expected research results will provide efficient and performanceguaranteed methods for order reduction and analysis of VLSI interconnectcircuits, and their corresponding algorithms and software for simulationtest. It will also contribute to engineering and science aspects by theexpected research results and software, as well as to graduate education.