Collaborative Research: Numerical Computations of Parasitic Parameters with Spectral Stochastic Collocation Methods for Nano-VLSI Technologies

随着VLSI技术缩小到45nm及以下的特征尺寸，光刻工艺不再能够在硅片中产生理想的电路元件形状/尺寸。在70nm技术下，几何参数的变化可以达到35%，并且随着特征尺寸的不断减小而变得越来越严重。相应的电参数变化将显著影响超大规模集成电路的性能和功能。因此，计算和分析硅片内寄生参数的统计特性成为新兴的纳米级超大规模集成电路技术的必然。该基金旨在开发随机计算方法，以解决纳米VLSI技术中分布更真实的更一般的随机变量。本项目将采用稀疏网格谱随机配置法开发高效算法，采用Wiener-Askey混沌基计算互连电容和电感，构建合适的非高斯随机变量随机计算方法。智力上的优点来自于复杂的随机理论的发展和最先进的工程问题的有效计算算法。本研究将提出基本的指导思想，并在实际工程问题上检验方法。该研究的广泛影响为随机过程变化寄生参数的计算开辟了新的研究方向。研究结果将对未来纳米级VLSI电路的寄生参数提取、电路仿真和设计产生重要影响。它将导致实用和高效的算法和CAD工具。本项目的研究将纳入应用数学和电气工程专业博士生的研究生教育，开发的软件将向社会公开。

As the VLSI technology scales down to 45nm feature size and below, the lithography process no longer produces the ideal shape/dimension of circuit components in a silicon wafer. Geometrical parameter variations at 70nm technology can reach as much as 35%, and become increasingly severe as the feature size continues to decrease. The corresponding electrical parameter variations will significantly affect the performance and function of a VLSI circuit. Therefore, computing and analyzing the statistical properties of parasitic parameters in a silicon wafer become inevitable to the emerging nanometer scale VLSI technology. This grant aims to develop stochastic computational methods to address more general stochastic variables with distributions more realistic in nanometer VLSI technology. This project will develop efficient algorithms using sparse grid spectral stochastic collocation method and compute interconnect capacitance and inductance using Wiener-Askey chaos basis and construct proper stochastic computational methods for non-Gaussian random variables. The intellectual merit comes from the development of sophisticated stochastic theories and efficient computing algorithms for the state-of-the-art engineering problems. This research will lay out basic guidelines and ideas and test the methods on realistic engineering problems. The broader impact of the research opens a new research direction in computing parasitic parameters with random process variations. The result of this research will have a great impact on the parasitic parameter extraction, circuit simulation and design of future nanometer scale VLSI circuits. It will lead to practical and efficient algorithms and CAD tools. Research of this project will be integrated into the graduate education of the Ph.D. students in applied mathematics and electrical engineering, and the developed software will be made public.