Collaborative Research: Numerical Computations of Parasitic Parameters with Spectral Stochastic Collocation Methods for Nano-VLSI Technologies

随着超大规模集成电路技术缩小到45纳米及以下的特征尺寸，光刻工艺不再在硅晶片中产生电路元件的理想形状/尺寸。70 nm技术的几何参数变化可以达到35%，并且随着特征尺寸的不断减小而变得越来越严重。相应的电参数变化将显著影响VLSI电路的性能和功能。因此，计算和分析硅片中寄生参数的统计特性成为新兴的纳米尺度超大规模集成电路技术的必然。这项资助旨在开发随机计算方法，以解决更一般的随机变量与分布更现实的纳米超大规模集成电路技术。 本计画将利用稀疏网格谱随机配置法发展有效的演算法，并利用Wiener-Askey混沌基计算互连线电容与电感，并针对非高斯随机变数建构适当的随机计算方法。智能的优点来自于先进的随机理论和有效的计算算法的国家的最先进的工程问题的发展。这项研究将奠定基本的指导方针和思想，并测试实际工程问题的方法。更广泛的影响，研究开辟了一个新的研究方向，在计算寄生参数与随机过程变化。本文的研究成果对未来纳米级超大规模集成电路的寄生参数提取、电路仿真和设计具有重要的指导意义。这将导致实用和高效的算法和CAD工具。该项目的研究将纳入博士研究生教育。应用数学和电子工程专业的学生，开发的软件将公开。

As the VLSI technology scales down to 45nm feature size and below, the lithography process no longer produces the ideal shape/dimension of circuit components in a silicon wafer. Geometrical parameter variations at 70nm technology can reach as much as 35%, and become increasingly severe as the feature size continues to decrease. The corresponding electrical parameter variations will significantly affect the performance and function of a VLSI circuit. Therefore, computing and analyzing the statistical properties of parasitic parameters in a silicon wafer become inevitable to the emerging nanometer scale VLSI technology. This grant aims to develop stochastic computational methods to address more general stochastic variables with distributions more realistic in nanometer VLSI technology. This project will develop efficient algorithms using sparse grid spectral stochastic collocation method and compute interconnect capacitance and inductance using Wiener-Askey chaos basis and construct proper stochastic computational methods for non-Gaussian random variables. The intellectual merit comes from the development of sophisticated stochastic theories and efficient computing algorithms for the state-of-the-art engineering problems. This research will lay out basic guidelines and ideas and test the methods on realistic engineering problems. The broader impact of the research opens a new research direction in computing parasitic parameters with random process variations. The result of this research will have a great impact on the parasitic parameter extraction, circuit simulation and design of future nanometer scale VLSI circuits. It will lead to practical and efficient algorithms and CAD tools. Research of this project will be integrated into the graduate education of the Ph.D. students in applied mathematics and electrical engineering, and the developed software will be made public.