CAREER: Memory Controller Interconnect and Policy Determination

在过去的15年里，微处理器和存储系统周期之间的差距一直在扩大。在实践中，由于处理器和DRAM之间的存储器层次结构和互连总线中的许多级别，从请求到响应，主存储器访问可能需要200个处理器时钟周期；超过50%的延迟是由于存储器层次结构和互连。这项研究将集中在通过新的互连技术来降低这一比例，并增加对DRAM控制器管理策略的关注。随着DRAM设备中存在的状态量的增加，可用的内存控制器策略决策集也会增加；这种增加的灵活性允许智能内存控制器优化控制器策略，以实现更高的性能。这项研究将考察当存储器控制器从静态控制策略改变为动态控制方案时，性能改善的潜力。这种影响将在各种互连拓扑上进行模拟，从当前的北桥到具有多条DRAM总线的CMP架构。

The gap between microprocessor and memory system cycle times has been increasing over the past 15 years. In practice, because of the many levels in the memory hierarchy and interconnection busses between the processor and DRAM, a primary memory access may take 200 processor clock cycles from request to response; more than 50% of this latency is due to the memory hierarchy and interconnect. This research will focus upon the reduction of this fraction by novel interconnect techniques and increasedfocus on the DRAM controller management policies. As the amount of state present in DRAM devices increases, the available set of memory controller policy decisions also increases; this increased flexibility allows an intelligent memory controller to optimize controller policies to achieveincreased performance. This research will examine the potential for improved performance when the memory controller changes from a static control policy to a dynamic control scheme. This impact will be simulated over a variety of interconnection topologies from the current NorthBridge to a CMP architecture with multiple DRAM busses.