CAREER: Memory Controller Interconnect and Policy Determination

在过去的15年中，微处理器和存储器系统周期时间之间的差距一直在增加。在实践中，由于内存层次结构中的许多级别以及处理器和DRAM之间的互连总线，主内存访问从请求到响应可能需要200个处理器时钟周期;超过50%的延迟是由于内存层次结构和互连。这项研究将集中在减少这一部分的新的互连技术，并越来越多地关注DRAM控制器管理策略。随着DRAM设备中存在的状态量的增加，可用的存储器控制器策略决策集也增加;这种增加的灵活性允许智能存储器控制器优化控制器策略以提高性能。本研究将探讨当记忆体控制器从静态控制策略改变为动态控制方案时，改善效能的潜力。这种影响将被模拟在各种互连拓扑结构，从目前的北桥到CMP架构与多个DRAM总线。

The gap between microprocessor and memory system cycle times has been increasing over the past 15 years. In practice, because of the many levels in the memory hierarchy and interconnection busses between the processor and DRAM, a primary memory access may take 200 processor clock cycles from request to response; more than 50% of this latency is due to the memory hierarchy and interconnect. This research will focus upon the reduction of this fraction by novel interconnect techniques and increasedfocus on the DRAM controller management policies. As the amount of state present in DRAM devices increases, the available set of memory controller policy decisions also increases; this increased flexibility allows an intelligent memory controller to optimize controller policies to achieveincreased performance. This research will examine the potential for improved performance when the memory controller changes from a static control policy to a dynamic control scheme. This impact will be simulated over a variety of interconnection topologies from the current NorthBridge to a CMP architecture with multiple DRAM busses.