CAREER: Formal Methods for Silicon Complexity in Nanometer VLSI Design

超大规模集成电路（VLSI）设计生产力危机，也就是说，可用晶体管的数量增长速度远远快于设计它们的能力，这已经成为半导体行业增长的最大威胁。硅的复杂性，指的是以前可以忽略的物理现象的影响，是这场危机的中心。基于我们的信念，提高生产率的唯一有效方法是将设计复杂性保持在可管理的水平，并且形式化方法是复杂性控制的正确技术，本研究的目的是通过将形式化方法应用于硅复杂性问题（如电感/电容耦合和过程变量）来提高设计生产率。该研究通过形式化方法的应用开发了方法论、模型和算法来处理硅的复杂性。通过将时序分析视为电路语义的提取，开发了一种同时处理电感和电容耦合延迟变化的时序分析系统。该系统开发和使用了一系列具有不同精度和复杂性的电感耦合模型。在此基础上，为库描述和IP规范创建了耦合延迟的时序宏模型。开发了时钟调度和重定时算法来分离信号切换时间以进行耦合延迟优化。信号交换时间信息也探讨在布线和放置，以尽量减少耦合之间的敏感导线。针对过程变异性，建立统计模型并将其结合到时序分析系统中计算电路的统计性能，并采用随机优化方法对统计性能进行优化。综合教育活动旨在计算机工程教育的两个方面：1)教育学生非正式方法，特别是它们在纳米超大规模集成电路设计中的应用，从而将所需的数学严谨性引入该学科；2)向学生介绍硅的复杂性及其对超大规模集成电路设计的影响，使他们具备现代高性能超大规模集成电路设计的必要背景。

The VLSI design productivity crisis, that is, the fact that the number ofavailable transistors grows much faster than the ability to design themmeaningfully, has become the greatest threat to the growth of semiconductorindustry. Silicon complexity, which refers to the impact of previously ignorable physical phenomena, is at the center of this crisis. Based on our beliefs thatthe only effective way to improve productivity is to maintain design complexityat a manageable level, and that formal methods are the right techniques forcomplexity control, the objective of this research is to improve designproductivity by applying formal methods to silicon complexity problems such asinductive/capacitive couplings and process variabilities.The research develops methodology, models, and algorithms to handle siliconcomplexity through the application of formal methods. By treating timing analysis as extracting semantics of a circuit, a timing analysis system is developed that handles both inductive and capacitive coupling delay variations. The systemdevelops and uses a range of inductive coupling models with different accuracyand complexity. Based on that, timing macromodels for coupling delays are created for library characterization and IP specification. Clock scheduling and retiming algorithms are developed to separate signal switching times for coupling delayoptimization. Signal switching time information is also explored in routing andplacement to minimize coupling between sensitive wires. For process variability, statistical models are developed and combined into the timing analysis system to compute the statistical performance of a circuit, and stochastic optimization is used to optimize the statistical performance. The integrated education activities aim at two aspects of computer engineering education: 1) educating students informal methods, especially their applications to nanometer VLSI design, thusbringing needed mathematical rigor into the discipline; 2) introducing studentsto silicon complexity and its impacts on VLSI design so that they are equippedwith necessary background for modern high performance VLSI design.