CAREER: Formal Methods for Silicon Complexity in Nanometer VLSI Design

超大规模集成电路设计生产率危机，即可用晶体管数量的增长速度远远快于有意义地设计它们的能力，已成为晶体管行业增长的最大威胁。硅的复杂性，指的是以前可解释的物理现象的影响，是这场危机的核心。基于我们的信念，即提高生产率的唯一有效途径是将设计复杂性保持在可管理的水平，以及形式化方法是控制复杂性的正确技术，本研究的目标是通过将形式化方法应用于硅复杂性问题，如电感/电容耦合和工艺可变性，来提高设计生产率。和算法来处理硅的复杂性，通过应用形式化的方法。通过将时序分析视为提取电路的语义，开发了一个时序分析系统，该系统可以处理电感和电容耦合延迟变化。该系统开发并使用了一系列具有不同精度和复杂性的电感耦合模型。在此基础上，建立了耦合延迟的时序宏模型，用于库表征和IP规范。时钟调度和重定时算法被开发来分离信号切换时间以用于耦合延迟优化。信号切换时间信息也被探索在路由和布局，以尽量减少敏感线之间的耦合。对于工艺可变性，统计模型被开发并结合到时序分析系统中以计算电路的统计性能，并且随机优化被用于优化统计性能。综合教育活动主要针对计算机工程教育的两个方面：1）教育学生非正式方法，特别是它们在纳米VLSI设计中的应用，从而将所需的数学严谨性引入学科; 2）向学生介绍硅的复杂性及其对VLSI设计的影响，从而使他们具备现代高性能VLSI设计的必要背景。

The VLSI design productivity crisis, that is, the fact that the number ofavailable transistors grows much faster than the ability to design themmeaningfully, has become the greatest threat to the growth of semiconductorindustry. Silicon complexity, which refers to the impact of previously ignorable physical phenomena, is at the center of this crisis. Based on our beliefs thatthe only effective way to improve productivity is to maintain design complexityat a manageable level, and that formal methods are the right techniques forcomplexity control, the objective of this research is to improve designproductivity by applying formal methods to silicon complexity problems such asinductive/capacitive couplings and process variabilities.The research develops methodology, models, and algorithms to handle siliconcomplexity through the application of formal methods. By treating timing analysis as extracting semantics of a circuit, a timing analysis system is developed that handles both inductive and capacitive coupling delay variations. The systemdevelops and uses a range of inductive coupling models with different accuracyand complexity. Based on that, timing macromodels for coupling delays are created for library characterization and IP specification. Clock scheduling and retiming algorithms are developed to separate signal switching times for coupling delayoptimization. Signal switching time information is also explored in routing andplacement to minimize coupling between sensitive wires. For process variability, statistical models are developed and combined into the timing analysis system to compute the statistical performance of a circuit, and stochastic optimization is used to optimize the statistical performance. The integrated education activities aim at two aspects of computer engineering education: 1) educating students informal methods, especially their applications to nanometer VLSI design, thusbringing needed mathematical rigor into the discipline; 2) introducing studentsto silicon complexity and its impacts on VLSI design so that they are equippedwith necessary background for modern high performance VLSI design.