SHF: Small: Collaborative Research: A Systematic Approach to Multicore Parallel CAD

SHF：小型：协作研究：多核并行 CAD 的系统方法

• 批准号: 1115550
• 负责人: Hai Zhou
• 金额: $ 24万
• 依托单位: Northwestern University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-09-01 至 2015-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1115550&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Systematic

This project aims at a systematic approach that integrates multi-level IC design automation flow by leveraging the parallel computational power in current and upcoming multi-core/many-core processors. The main challenge in this approach is to provide responsive high-level design decisions while incurring the massive computational cost of lower-level design algorithms. Fortunately, recent trends in processor architectures provide a solution. Compared with traditional uniprocessor systems, emerging multi-core/many-core microprocessors have far more computational power but limited global memory access capabilities. Parallel computational power may make it possible to break the boundaries of the existing IC design hierarchy and to vertically integrate the IC optimization fow. The potential benefits of an integrated solution are significant - accurate high-level design decisions become possible as low-level design details are derived concurrently, and low-level designs can also greatly benefit from high-quality high-level decisions. Together, an efficient and high-quality design flow becomes feasible, making design closure faster, thus saving time and reducing costs. The proposed work has the potential to overcome the key limitations of existing hierarchical IC CAD technologies and enable new IC design automation solutions, which in turn can benefit the IC and semiconductor industry. The PIs will work together with their industrial collaborators to develop and commercialize the proposed work. The project will have beneficial impact on education. The PIs intend to educate the next generation of software developers and practicing engineers in the design and innovation of IC design automation and parallel computing.

该项目旨在通过利用当前和即将推出的多核/众核处理器中的并行计算能力来集成多层IC设计自动化流程的系统方法。这种方法的主要挑战是提供响应的高级设计决策，同时招致低级设计算法的大量计算成本。幸运的是，处理器架构的最新趋势提供了解决方案。与传统的单处理器系统相比，新兴的多核/众核微处理器具有更强的计算能力，但全局存储器访问能力有限。并行计算能力可以打破现有集成电路设计层次的边界，并垂直集成集成电路优化流程。集成解决方案的潜在优势是显著的--由于同时获得低级设计细节，因此可以做出准确的高级设计决策，并且低级设计也可以从高质量的高级决策中受益匪浅。这样一来，高效、高质量的设计流程就变得可行，从而使设计更快地完成，从而节省时间并降低成本。拟议的工作有可能克服现有分层IC CAD技术的关键限制，并实现新的IC设计自动化解决方案，这反过来又可以使IC和半导体行业受益。PI将与他们的工业合作者一起开发和商业化拟议的工作。该项目将对教育产生有益的影响。PI旨在教育下一代软件开发人员和实践工程师在IC设计自动化和并行计算的设计和创新。