The Nano-Precision HARPSS-CMOS Process for RF and Sensory Microsystems

用于射频和传感微系统的纳米精度 HARPSS-CMOS 工艺

• 批准号: 0301900
• 负责人: Farrokh Ayazi
• 金额: $ 27.03万
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-05-01 至 2007-04-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0301900&HistoricalAwards=false
• 关键词: Nano; Precision; HARPSS; CMOS; Process

0301900AyaziThis proposal is aimed at the integration of a high aspect-ratio, sub-100nm vertical airgapMEMS/NEMS technology with a 1um gate-length CMOS process, and the application of theresulting high aspect ratio CMOS-MEMS process to high-performance RF-sensory microsystems,as well as mixed-signal circuits. The implementation of the following two testbeds is proposed astechnology demonstrators:1. The high-performance sensor system testbed: Implementation of a novel CMOS-integratedinertial-grade (sub-ug resolution) acceleration/vibration sensor system with direct digital output.This single-chip sensor system will have 3-4 orders of magnitude higher sensitivity compared tothe current state of the art integrated microsystem. It consists of a nano-precision lateralaccelerometer and a high-performance mixed-signal interface circuit which utilizes 200um tallvertical poly-poly capacitors, yielding 2 orders of magnitude reduction in the die area.2. The wireless RF components testbed: Implementation of MEMS-based high-Q on-chipfrequency references "over a wide frequency range extending into GHz" integrated with CMOSelectronics (MEMS-based VCO).Over the past few decades, CMOS and CMOS-like processes have substantially grown in thenumber and thickness of the deposited layers on the surface of the Si substrate (the so-calledback-end processes). However, the front-end processes have not grown proportionally andremained limited to the steps necessary to create the transistors. The out of silicon thickness ofCMOS has grown to be almost an order of magnitude larger than the inside silicon thickness of it.The development of the integrated MEMS processes has followed the same model withintegration of surface micromachined structures. The question is: can the front-end of the CMOSprocess be modified to bring new life to integrated MEMS by enhancing the performance andproviding higher levels of functionality?The intellectual merit of the proposed activity is to modify the front-end of the CMOSprocess using the deep reactive ion etching and refill technique to make use of the thirddimension into the silicon and embed functionality (both electrical and mechanical) inside theCMOS-grade silicon substrate. The proposed process will allow the scaling of micromechanicalstructures into the nanometer domain through its unique ability to create sub-100nm vertical gapsand sub-micron silicon features. High aspect ratio poly and single crystal silicon structures (withhigh quality factors) separated by nanometer in size gaps will be integrated with CMOS circuits.The broader impact resulting from the proposed activity is the ability to bring about significantly higher levels of performance and integration to the integrated MEMS and mixed-signal circuits. Higher performance levels and the ability to communicate wireless on a single silicon chip can open up the door to new opportunities and applications. Imagine having a tiny MEMS-CMOS silicon chip that can not only monitor very small changes in the environment, but also can transmit the monitored data real time in digital form to a receiver base, or communicate with a network of wireless sensory nodes. Such wireless sensory nodes can find numerous applications in various forms of environmental monitoring and energy-efficient systems.

0301900 Ayazi该提案旨在将高深宽比、亚100 nm垂直气隙MEMS/NEMS技术与1 μ m栅长CMOS工艺集成，并将由此产生的高深宽比CMOS-MEMS工艺应用于高性能RF传感微系统以及混合信号电路。以下两个测试平台的实施被建议作为技术示范：1.高性能传感器系统测试平台：实现一种新型CMOS集成惯性级（亚μ g分辨率）加速度/振动传感器系统，具有直接数字输出。与当前最先进的集成微系统相比，这种单芯片传感器系统的灵敏度将提高3-4个数量级。它由一个纳米精度横向加速度计和一个高性能的混合信号接口电路组成，该电路采用200 μ m高垂直多晶硅-多晶硅电容，使芯片面积减少了2个数量级.无线射频元件测试平台：与CMOS电子集成的MEMS高Q片上频率基准的实现（MEMS VCO）在过去的几十年里，CMOS和CMOS类工艺在硅衬底表面沉积层的数量和厚度（所谓的后端工艺）方面有了很大的发展。然而，前端工艺并没有按比例增长，仍然局限于制造晶体管所需的步骤。CMOS的外部硅厚度已经比内部硅厚度大了近一个数量级，MEMS集成工艺的发展也遵循了表面微机械结构集成的模式。问题是：能否通过改进CMOS工艺的前端，提高性能并提供更高水平的功能，从而为集成MEMS带来新的生命？拟议活动的智力价值是修改CMOS工艺的前端，使用深反应离子蚀刻和再填充技术，以利用第三维到硅和嵌入功能（电气和机械）内的CMOS级硅基板。提出的工艺将允许通过其独特的能力，以创建亚100纳米的垂直间隙和亚微米硅功能的micromechanicalstructures到纳米域的缩放。高纵横比的多晶硅和单晶硅结构（具有高品质因数）将与CMOS电路集成在一起，这些结构之间的间距为纳米级，所提出的活动产生的更广泛的影响是能够为集成MEMS和混合信号电路带来更高水平的性能和集成度。更高的性能水平和在单个硅芯片上进行无线通信的能力可以为新的机会和应用打开大门。想象一下，有一个微小的MEMS-CMOS硅芯片，不仅可以监测环境中非常微小的变化，而且可以将监测到的数据以数字形式真实的时间传输到接收器基地，或者与无线传感节点网络进行通信。这种无线传感节点可以在各种形式的环境监测和节能系统中找到许多应用。