HiPHiPECS: High Level Programming of High Performance Embedded Computing Systems
HiPHiPECS:高性能嵌入式计算系统的高级编程
基本信息
- 批准号:0306142
- 负责人:
- 金额:--
- 依托单位:
- 依托单位国家:美国
- 项目类别:Continuing Grant
- 财政年份:2003
- 资助国家:美国
- 起止时间:2003-07-15 至 2007-06-30
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
0306142Sanjay RajopadhyeColorado State UniversityHiPHiPECS: High Level Prgramming of High Performance Embedded Computing Systems$497,232This project addresses curriculum development in the field of embedded computing which requires expertise from a number of disciplines: digital circuit design, VLSI, real time systems, applications, algorithms and programming. Of the two major classes of embedded systems, one consists of extremely large volumes of simple embedded systems (toasters, doorknobs, toys, controllers, etc.), and typically does not require high performance. The devices are inexpensive, mature, and stable, cross-compilation environments exist and so products can be designed and marketed fairly reliably. This project, HiPHiPECS, focuses on a related, more challenging and growing segment of the market (telephones, digital cameras, automobile sensor data processing, satellite control, information appliances, network routers, photocopiers, printers, scanners, fax machines, etc.), that require extremely high performance. Developing these high performance embedded applications necessitates the exploitation of parallelism, imposes increasingly severe constraints on bandwidth, power/energy consumption, computation time, and throughput. For such systems, there is an increasing trend towards Systems-on-a-Chip (SoC) where multiple implementation fabrics (re-configurable logic, processor cores, DSP 's and ASIC 's) are combined on a single heterogeneous chip. According to the International Technology Roadmap for Semiconductors (ITRS), there is an exponential "design gap" (the roadmap identifies this as the gap between the ability of circuit designers to effectively use silicon resources and the number of transistors available on the chip) in this area. This design gap necessitates raising the level of abstraction involved in digital circuit/system design. Although this has been identified as a need, few efforts are directed toward addressing the associated educational and training needs in a concerted manner. There is a critical need to train circuit/system designers in these skills that encompass such areas as: Expertise in the application domain (signal/image processing, networking, control systems, numerical analysis, algorithms), System engineering and design (software engineering, modularity, stepwise refinement, formal methods for correctness), Programming skills, data structures, algorithm analysis, Parallel processing (parallel algorithm theory, parallelism detection, parallel programming languages, multi-threading, data-parallelism), Operating systems, especially real-time OS, Computer architecture, instruction set architectures, DSP 's, instruction level parallelism, and SIMD architectures, Circuit level design, performance analysis, precise modeling of power/energy consumption, throughput, area and time. The main contributions of HiPHiPECS will be the development of a curriculum for high performance embedded systems. It will target FPGA based re-configurable computing platforms, since their re-configurability allows for the exploration of other implementation fabrics in a pedagogic setting. The proposed curriculum will focus on the computation-and data-intensive parts of embedded applications, primarily because this is where high performance solutions are critical, with the goal of enhancing instruction in the area of High Level Programming for High Performance Embedded Computing Systems. The project, which involves industrial collaboration, addresses a critical national need, it is founded on current research in High Performance Computing, and it represents a major shift (as opposed to an incremental change) in education in this area.
0306142 Sanjay Rajopadhye科罗拉多州立大学HiPHiPECS:高性能嵌入式计算系统的高级编程$497,232该项目涉及嵌入式计算领域的课程开发,需要来自多个学科的专业知识:数字电路设计,VLSI,真实的时间系统,应用程序,算法和编程。在嵌入式系统的两大类中,一类是由大量简单的嵌入式系统(烤面包机、门把手、玩具、控制器等)组成,并且通常不需要高性能。这些设备价格便宜,成熟,稳定,存在交叉编译环境,因此可以相当可靠地设计和销售产品。该项目HiPHiPECS专注于相关的、更具挑战性且不断增长的市场领域(电话、数码相机、汽车传感器数据处理、卫星控制、信息家电、网络路由器、复印机、打印机、扫描仪、传真机等),这需要极高的性能。开发这些高性能的嵌入式应用程序需要开发并行性,对带宽,功耗/能耗,计算时间和吞吐量施加越来越严格的约束。对于这样的系统,存在向片上系统(SoC)的增长趋势,其中多个实现结构(可重新配置的逻辑、处理器核、DSP和ASIC)被组合在单个异构芯片上。根据国际半导体技术路线图(ITRS),该领域存在指数级的“设计差距”(路线图将其确定为电路设计人员有效利用硅资源的能力与芯片上可用的晶体管数量之间的差距)。)。这种设计差距需要提高数字电路/系统设计中涉及的抽象水平。虽然这已被确定为一种需要,但很少有努力以协调一致的方式解决相关的教育和培训需要。迫切需要对电路/系统设计人员进行这些技能的培训,这些技能包括以下领域:应用领域的专业知识(信号/图像处理、网络、控制系统、数值分析、算法)、系统工程与设计(软件工程,模块化,逐步求精,正确性的形式化方法),编程技巧,数据结构,算法分析,并行处理(并行算法理论、并行性检测、并行编程语言、多线程、数据并行性),操作系统,特别是实时OS,计算机体系结构、指令集体系结构、DSP、指令级并行性和SIMD体系结构,电路级设计,性能分析,功率/能量消耗的精确建模,吞吐量,地区和时间。HiPiPECS的主要贡献将是开发高性能嵌入式系统的课程。它将针对基于FPGA的可重新配置的计算平台,因为它们的可重新配置性允许在教学环境中探索其他实施结构。拟议的课程将侧重于嵌入式应用程序的计算和数据密集型部分,主要是因为这是高性能解决方案至关重要的地方,其目标是增强高性能嵌入式计算系统高级编程领域的教学。该项目涉及工业合作,解决了一个关键的国家需求,它建立在高性能计算的当前研究基础上,它代表了这一领域教育的重大转变(而不是渐进式变化)。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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Sanjay Rajopadhye其他文献
Special Issue on ASAP 2004 Conference
- DOI:
10.1007/s11265-007-0133-y - 发表时间:
2007-09-13 - 期刊:
- 影响因子:1.800
- 作者:
Joseph R. Cavallaro;Sanjay Rajopadhye;Lothar Thiele;Tobias Noll - 通讯作者:
Tobias Noll
Monoparametric Tiling of Polyhedral Programs
- DOI:
10.1007/s10766-021-00694-2 - 发表时间:
2021-03-18 - 期刊:
- 影响因子:0.900
- 作者:
Guillaume Iooss;Christophe Alias;Sanjay Rajopadhye - 通讯作者:
Sanjay Rajopadhye
OREGAMI: Tools for mapping parallel computations to parallel architectures
- DOI:
10.1007/bf01379319 - 发表时间:
1991-06-01 - 期刊:
- 影响因子:0.900
- 作者:
Virginia M. Lo;Sanjay Rajopadhye;Samik Gupta;David Keldsen;Moataz A. Mohamed;Bill Nitzberg;Jan Arne Telle;Xiaoxiong Zhong - 通讯作者:
Xiaoxiong Zhong
Quasi-Linear allocation functions for efficient array design
- DOI:
10.1007/bf00925116 - 发表时间:
1992-05-01 - 期刊:
- 影响因子:1.800
- 作者:
Xiaoxiong Zhong;Sanjay Rajopadhye - 通讯作者:
Sanjay Rajopadhye
Sanjay Rajopadhye的其他文献
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{{ truncateString('Sanjay Rajopadhye', 18)}}的其他基金
Co-Design for Exascale General Purpose computing on Graphics Processing Units (GPGPU)
图形处理单元 (GPGPU) 上百亿亿次级通用计算的协同设计
- 批准号:
1240991 - 财政年份:2012
- 资助金额:
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国际:美国学生在 INRIA 的研究经验 - REUSSI 2
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1045885 - 财政年份:2010
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Continuing Grant
CPA-CPL: The Reduction Simplification Engine
CPA-CPL:简化简化引擎
- 批准号:
0811852 - 财政年份:2008
- 资助金额:
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Research Initiation: Mechanical Synthesis of Systolic Arrays
研究启动:脉动阵列的机械合成
- 批准号:
8802454 - 财政年份:1988
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