Hybrid External/Built-In Self-Test Techniques

随着测试新一代复杂片上系统（SOC）设计所需的测试数据量持续快速增长，其中所有测试数据存储在测试器上并传送到芯片/从芯片传送的常规外部测试方法变得越来越困难。 测试仪的速度、内存和I/O通道有限。 测试仪和芯片之间有限的测试数据带宽正在成为一个主要的瓶颈，预计会变得更糟。 该项目涉及开发混合方案，以新颖的方式将联合收割机外部测试和自测试方法相结合，以减轻外部测试人员的负担。这些技术可以提供两全其美的效果。 自测试方法的开销和故障覆盖率限制可以通过智能地利用来自测试仪的确定性数据来指导自测试硬件来克服，而外部测试仪的测试数据带宽和存储要求可以减少几个数量级。 本研究所要回答的问题包括：1。使用测试仪的确定性数据来指导芯片上的测试模式生成硬件的最有效方法是什么。在测试数据带宽受限的情况下，如何最小化硬件.对于多核系统芯片（SOC），为每个核配置混合测试硬件的最佳方法是什么？如何使用测试仪的确定性数据来降低自测试过程中的功耗。如何用混合方案提高延迟故障覆盖率。

As the amount of test data required to test new generations of complex system-on-chip (SOC) designs continues to grow rapidly, conventional external testing approaches where all test data is stored on the tester and transferred to/from the chip is becoming increasingly difficult. Testers have limited speed, memory, and I/O channels. The limited test data bandwidth between the tester and the chip is becoming a major bottleneck that is projected to become much worse. This project involves developing hybrid schemes that combine external testing and self-testing approaches in novel ways to ease the burden on the external tester. Such techniques can provide the best of both worlds. The overhead and fault coverage limitations of self-test approaches can be overcome by intelligently making use of deterministic data from the tester to guide the self-test hardware, while the test data bandwidth and storage requirements for the external tester can be reduced by orders of magnitude. Some of the questions to be answered in this research include: 1. What are the most efficient ways to use deterministic data from the tester to guide test pattern generation hardware on the chip.2. How to minimize the hardware under a constraint on test data bandwidthfrom the tester.3. For a system-on-chip (SOC) with multiple cores, what is the best way toconfigure the hybrid test hardware for each core.4. How can deterministic data from the tester be used to reduce powerdissipation during self-test.5. How can delay fault coverage be improved with a hybrid scheme.