Novel CMOS Circuit Design Techniques for Multi-Gb/s Broadband Communications Circuits

这个项目需要研究新的设计技术，以提高CMOS宽带电路的速度和性能。为了提高基本宽带结构的速度性能，提出了使用分布式放大器结构，包括时钟分频器和2对1选择电路。初步结果表明，采用0.18 u CMOS工艺设计的分布式时钟分配器可以在超过32GHz的输入时钟频率下工作。采用相同技术的2对1多路复用器可以以20Gb/s的比特率运行。这些分布式模块的速度能力是使用传统集总电路设计技术所能达到的速度的两倍。使用分布式结构的另一个显著优点是，可以将输出传输线设计为与输出终端相匹配，从而消除了对专用输出缓冲区的需求。这反过来又可以显著节省电力。高速时钟/数据恢复（CDR）电路的设计既困难又复杂。特别是，在低抖动和大频率锁定范围之间有一个关键的权衡。许多CDR设计通过使用双环架构来解决这一冲突。一个环路用于锁定频率（通常需要参考时钟输入）；另一个环路包含低抖动CDR。这些架构带来了大量的复杂性，并消耗了大量的功率。在这个建议中，我们提出了一种新的CDR电路，它结合了线性和二进制鉴相器的优点，从而可以实现低抖动和高频率锁定范围。提议的CDR自然包含直流控制电压，允许其鉴相器特性根据这两个规范进行优化。由于广域网的大部分性能瓶颈是在电子元件而不是光纤本身，因此拟议的研究将通过在光通信系统中设计更快和更高性能的电路，对有线通信基础设施产生重大影响。其他通信系统，如千兆以太网和光纤通道，也将得到类似的增强。

This project entails the investigation of new design techniques that enhance the speed and performance of CMOS broadband circuits.The use of distributed amplifier structures is proposed to increase the speed performance of elementary broadband structures, including clock divider and 2-to-1 select circuit. Preliminary results suggest that a distributed clock divider designed using a 0.18 u CMOS process can function with an input clock frequency of over 32GHz.A 2-to-1 multiplexer built in the same technology can operate at a bit rate of 20Gb/s.The speed capabilities of these distributed blocks is double what can be achieved using conventional lumped circuit design techniques. Another significant advantage of using distributed structures is that the output transmission line can be designed to match to the output termination, thereby eliminating the requirement for a dedicated output buffer. This in turn results in significant power savings.The design of high-speed clock/data recovery (CDR) circuits is difficult and complex. In particular, there is a critical trade-off between low jitter and large frequency locking range. Many CDR designs resolve this conflict by using a dual-loop architecture. One loop is used to lock the frequency (which often requires a reference clock input); the other loop incorporates the low-jitter CDR. These architectures entail a large amount of complexity and dissipate large power. In this proposal we present a novel CDR circuit that combines the advantages of linear and binary phase detectors so that both low jitter and high frequency locking range are possible. The proposed CDR naturally incorporates a dc control voltage that allows its phase detector characteristic to be optimized according to these two specifications.Since much of the performance bottleneck of wide-area networks is in the electronic components rather than the optical fiber itself, the proposed research will have a significant impact on wireline communications infrastructure by enabling the design of faster and higher performance circuits in optical communications systems. Other communications systems, such as gigabit ethernet and fiber channel, will be similarly enhanced.