Novel CMOS Circuit Design Techniques for Multi-Gb/s Broadband Communications Circuits

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This project entails the investigation of new design techniques that enhance the speed and performance of CMOS broadband circuits.The use of distributed amplifier structures is proposed to increase the speed performance of elementary broadband structures, including clock divider and 2-to-1 select circuit. Preliminary results suggest that a distributed clock divider designed using a 0.18 u CMOS process can function with an input clock frequency of over 32GHz.A 2-to-1 multiplexer built in the same technology can operate at a bit rate of 20Gb/s.The speed capabilities of these distributed blocks is double what can be achieved using conventional lumped circuit design techniques. Another significant advantage of using distributed structures is that the output transmission line can be designed to match to the output termination, thereby eliminating the requirement for a dedicated output buffer. This in turn results in significant power savings.The design of high-speed clock/data recovery (CDR) circuits is difficult and complex. In particular, there is a critical trade-off between low jitter and large frequency locking range. Many CDR designs resolve this conflict by using a dual-loop architecture. One loop is used to lock the frequency (which often requires a reference clock input); the other loop incorporates the low-jitter CDR. These architectures entail a large amount of complexity and dissipate large power. In this proposal we present a novel CDR circuit that combines the advantages of linear and binary phase detectors so that both low jitter and high frequency locking range are possible. The proposed CDR naturally incorporates a dc control voltage that allows its phase detector characteristic to be optimized according to these two specifications.Since much of the performance bottleneck of wide-area networks is in the electronic components rather than the optical fiber itself, the proposed research will have a significant impact on wireline communications infrastructure by enabling the design of faster and higher performance circuits in optical communications systems. Other communications systems, such as gigabit ethernet and fiber channel, will be similarly enhanced.