Novel CMOS Circuit Design Techniques for Multi-Gb/s Broadband Communications Circuits

用于多 Gb/s 宽带通信电路的新型 CMOS 电路设计技术

• 批准号: 0323349
• 负责人: Michael Green
• 金额: $ 27万
• 依托单位: University of California-Irvine
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-08-01 至 2007-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0323349&HistoricalAwards=false
• 关键词: Novel; CMOS; Circuit; Design; Techniques

This project entails the investigation of new design techniques that enhance the speed and performance of CMOS broadband circuits.The use of distributed amplifier structures is proposed to increase the speed performance of elementary broadband structures, including clock divider and 2-to-1 select circuit. Preliminary results suggest that a distributed clock divider designed using a 0.18 u CMOS process can function with an input clock frequency of over 32GHz.A 2-to-1 multiplexer built in the same technology can operate at a bit rate of 20Gb/s.The speed capabilities of these distributed blocks is double what can be achieved using conventional lumped circuit design techniques. Another significant advantage of using distributed structures is that the output transmission line can be designed to match to the output termination, thereby eliminating the requirement for a dedicated output buffer. This in turn results in significant power savings.The design of high-speed clock/data recovery (CDR) circuits is difficult and complex. In particular, there is a critical trade-off between low jitter and large frequency locking range. Many CDR designs resolve this conflict by using a dual-loop architecture. One loop is used to lock the frequency (which often requires a reference clock input); the other loop incorporates the low-jitter CDR. These architectures entail a large amount of complexity and dissipate large power. In this proposal we present a novel CDR circuit that combines the advantages of linear and binary phase detectors so that both low jitter and high frequency locking range are possible. The proposed CDR naturally incorporates a dc control voltage that allows its phase detector characteristic to be optimized according to these two specifications.Since much of the performance bottleneck of wide-area networks is in the electronic components rather than the optical fiber itself, the proposed research will have a significant impact on wireline communications infrastructure by enabling the design of faster and higher performance circuits in optical communications systems. Other communications systems, such as gigabit ethernet and fiber channel, will be similarly enhanced.

本计画主要研究提升CMOS宽频电路速度与效能的新设计技术，提出使用分散式放大器结构来提升基本宽频电路的速度效能，包括时钟分频器与二比一选择电路。 初步结果表明，采用0.18 u CMOS工艺设计的分布式时钟分频器可以在超过32 GHz的输入时钟频率下工作。采用相同技术构建的2比1多路复用器可以以20 Gb/s的比特率工作。这些分布式模块的速度能力是使用传统集总电路设计技术可以实现的两倍。 使用分布式结构的另一个显著优点是，输出传输线可以被设计为与输出端接匹配，从而消除了对专用输出缓冲器的需求。高速时钟/数据恢复（CDR）电路的设计是困难和复杂的。 特别地，在低抖动和大频率锁定范围之间存在关键的权衡。 许多CDR设计通过使用双环路架构来解决此冲突。 一个环路用于锁定频率（通常需要参考时钟输入）;另一个环路包含低抖动CDR。 这些架构需要大量的复杂性和消耗大量的功率。 在这个建议中，我们提出了一种新的CDR电路，结合了线性和二进制相位检测器的优点，使低抖动和高频率锁定范围是可能的。 所提出的CDR自然地结合了直流控制电压，使得其相位检测器特性能够根据这两个规范进行优化。由于广域网的大部分性能瓶颈在于电子元件而不是光纤本身，拟议中的研究将对有线通信基础设施产生重大影响，使设计更快、更高性能的光通信电路成为可能。通信系统。 其他通信系统，如千兆以太网和光纤通道，也将得到类似的增强。