Novel CMOS Circuit Design Techniques for Multi-Gb/s Broadband Communications Circuits

该项目需要研究新的设计技术来提高CMOS宽带电路的速度和性能，提出使用分布式放大器结构来提高基本宽带结构的速度性能，包括时钟分频器和2对1选择电路。初步测试结果表明，采用0.18u工艺设计的分布式时钟分配器的输入时钟频率可达32 GHz以上，采用该工艺设计的2对1多路复用器的比特率可达20 Gb/s，其速度性能是传统集总电路设计方法的两倍。使用分布式结构的另一个显著优点是，可以将输出传输线设计为与输出终端匹配，从而消除对专用输出缓冲器的要求。高速时钟/数据恢复(CDR)电路的设计是困难和复杂的。特别是，在低抖动和大频率锁定范围之间存在关键的权衡。许多CDR设计通过使用双环路架构来解决这一冲突。一个环路用于锁定频率(通常需要参考时钟输入)；另一个环路结合低抖动CDR。这些体系结构需要大量的复杂性，并耗费大量的电力。在该方案中，我们提出了一种新颖的CDR电路，它结合了线性鉴相器和二进制鉴相器的优点，从而可以同时实现低抖动和高频锁定范围。由于广域网络的大部分性能瓶颈在电子元件而不是光纤本身，因此该研究将对有线通信基础设施产生重大影响，从而能够在光通信系统中设计出更快、更高性能的电路。其他通信系统，例如千兆位以太网和光纤通道，也将得到类似的增强。

This project entails the investigation of new design techniques that enhance the speed and performance of CMOS broadband circuits.The use of distributed amplifier structures is proposed to increase the speed performance of elementary broadband structures, including clock divider and 2-to-1 select circuit. Preliminary results suggest that a distributed clock divider designed using a 0.18 u CMOS process can function with an input clock frequency of over 32GHz.A 2-to-1 multiplexer built in the same technology can operate at a bit rate of 20Gb/s.The speed capabilities of these distributed blocks is double what can be achieved using conventional lumped circuit design techniques. Another significant advantage of using distributed structures is that the output transmission line can be designed to match to the output termination, thereby eliminating the requirement for a dedicated output buffer. This in turn results in significant power savings.The design of high-speed clock/data recovery (CDR) circuits is difficult and complex. In particular, there is a critical trade-off between low jitter and large frequency locking range. Many CDR designs resolve this conflict by using a dual-loop architecture. One loop is used to lock the frequency (which often requires a reference clock input); the other loop incorporates the low-jitter CDR. These architectures entail a large amount of complexity and dissipate large power. In this proposal we present a novel CDR circuit that combines the advantages of linear and binary phase detectors so that both low jitter and high frequency locking range are possible. The proposed CDR naturally incorporates a dc control voltage that allows its phase detector characteristic to be optimized according to these two specifications.Since much of the performance bottleneck of wide-area networks is in the electronic components rather than the optical fiber itself, the proposed research will have a significant impact on wireline communications infrastructure by enabling the design of faster and higher performance circuits in optical communications systems. Other communications systems, such as gigabit ethernet and fiber channel, will be similarly enhanced.