Emerging devices integration above CMOS circuit

CMOS电路之上的新兴器件集成

• 批准号: RGPIN-2014-04293
• 负责人: Drouin, Dominique
• 金额: $ 2.7万
• 依托单位: Université de Sherbrooke
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2015
• 资助国家: 加拿大
• 起止时间: 2015-01-01 至 2016-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=587717
• 关键词: Emerging; devices; integration; above; CMOS

During the last 5 decades, the microelectronic industry has been able to drastically increase the computing performance while reducing the cost-per-chip. This outstanding improvement is essentially due to the scaling of the CMOS (Complementary Metal Oxide Semiconductor) technology. The International Technology Roadmap for Semiconductors (ITRS) anticipates that this trend or his equivalent in performance will continue for several years resulting ultimately in 5-7 nm gate transistors by 2025. This projection challenges the most optimistic prediction of transistor utilizing the CMOS physics for operation. Thus, innovative solutions must be introduced for post-CMOS technology in the midterm. Furthermore, the power density tendency of assembled modules is reaching level where standard air cooling is not adequate anymore. This energy consumption issue is becoming the predominant factor for introducing new devices. The industry is pursing different approaches for post-CMOS and equivalent performance enhancement. One solution for the former issue is the introduction of the very promising tunnel field effect transistor. For the latter one, tremendous effort have been deployed to increase the number of device by mm2 through 3D integration at the chip level. This proposed research program will address both issues by investigating innovative low-power nanoelectronics device that can be monolithically integrated in 3D with CMOS technology to investigate new functionalities and increase performance of logic and memory devices. The global objective is not to directly replace CMOS technology but rather complement it using back-end-of-line compatible devices. Such approach allows to i) increase devices density due to 3D integration, ii) reduce latency from shorter interconnections, iii) globally reduce energy consumption by reducing parasitic loss. During this 5 years project, we will develop two low-power nanoelectronic devices integrated above CMOS circuit. The silicon nanocrystal tunnel field effect transistor combines our nanodamascene process and amorphous silicon. The potential outcome of such device will be the realization of a low-power transistor operating at voltage below 0.5V with extremely low Ioff current due to tunneling through undoped channel. The second nanoelectronic device will also combine our nanodamascene process with indium oxide nanocrystals to realize embedded non-volatile memory. This two terminals memory has the advantage to be highly scalable and the potential to be embedded with microprocessor. The scientific and social impact of this research is ranging from more energy efficient portable electronic (tablet, smart phone) to universal memory (single memory type regrouping DRAM, hard-disk and flash memory).

在过去的 5 年里，微电子行业已经能够大幅提高计算性能，同时降低每芯片的成本。这种显着的改进主要归功于 CMOS（互补金属氧化物半导体）技术的微缩化。国际半导体技术路线图 (ITRS) 预计，这种趋势或同等性能将持续数年，最终到 2025 年将出现 5-7 nm 栅极晶体管。这一预测挑战了利用 CMOS 物理原理进行操作的晶体管的最乐观预测。因此，必须在中期推出后 CMOS 技术的创新解决方案。此外，组装模块的功率密度趋势已达到标准空气冷却不再足够的水平。这种能源消耗问题正在成为引入新设备的主要因素。业界正在寻求不同的方法来实现后 CMOS 和等效性能增强。前一问题的一个解决方案是引入非常有前途的隧道场效应晶体管。对于后者，我们付出了巨大的努力，通过芯片级的 3D 集成将器件数量增加了 2 mm2。 这项拟议的研究计划将通过研究创新的低功耗纳米电子器件来解决这两个问题，该器件可以与 CMOS 技术进行 3D 单片集成，以研究新功能并提高逻辑和存储器件的性能。 全球目标不是直接取代 CMOS 技术，而是使用后端兼容设备对其进行补充。这种方法可以 i) 由于 3D 集成而增加设备密度，ii) 减少较短互连带来的延迟，iii) 通过减少寄生损耗来全局降低能耗。在这个为期5年的项目中，我们将开发两种集成在CMOS电路之上的低功耗纳米电子器件。硅纳米晶体隧道场效应晶体管结合了我们的纳米镶嵌工艺和非晶硅。这种器件的潜在成果将是实现工作电压低于 0.5V 的低功率晶体管，并且由于通过未掺杂沟道的隧道效应而具有极低的 Ioff 电流。 第二个纳米电子器件还将我们的纳米镶嵌工艺与氧化铟纳米晶体相结合，以实现嵌入式非易失性存储器。这种两端存储器具有高度可扩展性和嵌入微处理器的潜力。这项研究的科学和社会影响范围从更节能的便携式电子产品（平板电脑、智能手机）到通用存储器（单一存储器类型重组 DRAM、硬盘和闪存）。