Control-Flow Processors

控制流处理器摘要提出了一种架构，统一细粒度的控制流和数据流的依赖关系，在当代超标量处理器的上下文中，保持高度精简的机制超标量处理器，同时赋予他们的可伸缩性。未来的独立指令被获取、执行和本地终结，它们的结果被传播并且相应的资源被释放，并且它们的累积效应被维持而不管先前未解决的分支误预测。分支错误预测不再串行化执行，留下异常和有限的资源作为系统中唯一剩下的串行化约束。在高性能微处理器领域（超级计算机、个人电脑、笔记本电脑甚至手机），仍然存在一些顽固的瓶颈，从根本上限制了性能，使得难以将额外晶体管的潜力转化为有效的性能提升。该项目更广泛的意义是一种方法，旨在克服在扩展微处理器性能方面剩余的巨大挑战问题之一。

Control-Flow ProcessorsAbstractAn architecture is presented that unifies fine-grain control-flow and data-flow dependences in the context of contemporary superscalar processors, preserving highly streamlined mechanisms of superscalar processors while endowing them with dataflow properties. Future independent instructions are fetched, executed, and locally finalized, their results propagated and corresponding resources freed, and their cumulative effects sustained regardless of prior unresolved branch mispredictions. Branch mispredictions no longer serialize execution, leaving exceptions and finite resources as the only remaining serializing constraints in the system.In the domain of high-performance microprocessors (which power supercomputers, personal computers, laptops, and even cell phones), there remain a few dogged bottlenecks that fundamentally constrain performance, making it difficult to translate the potential of additional transistors into effective performance gains. The project's broader significance is an approach that aims to overcome one of the remaining grand-challenge problems in scaling microprocessor performance.