CPA-CSA: FabScalar: A Standard Superscalar Library for Fabricating Heterogeneous Chip Multiprocessors

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Microprocessor designers have been able to periodically roll out new processors that double the performance of their predecessors, by leveraging underlying technology improvements and fundamentally redesigning the processor?s internal organization. This trend is abating. It is increasingly difficult to tap additional performance from a general-purpose processor by traditional technology and pipeline scaling. Researchers have begun rethinking the notion of general-purpose processor to mean many different processors on a single chip, each processor tailored to an individual application or a class of applications. Such a Heterogeneous Chip Multiprocessor (HCMP) can deliver higher overall performance with lower power consumption by exploiting customization and diversity: customizing processors to specific applications for higher performance and lower power, meanwhile providing enough different processors to broadly cover arbitrary applications.The HCMP concept has great potential but it is currently very impractical. Designing, verifying, and fabricating just one processor takes hundreds of engineers with highly specialized expertise up to five years to develop. An HCMP multiplies this effort by the number of different processor designs.The project addresses this overlooked challenge of HCMP research. The project explores a new approach to designing, verifying, and fabricating arbitrary superscalar processors, called FabScalar. The key idea is to develop a library of prefabricated canonical superscalar pipeline stages, in a wide variety of dimensions and features, enabling the automatic composition of arbitrary superscalar processors at the natural pipeline stage level. FabScalar is a first step for the practical development of true HCMPs. These HCMPs will provide a more efficient bridge between diverse applications and the underlying silicon.