CPA-CSA: FabScalar: A Standard Superscalar Library for Fabricating Heterogeneous Chip Multiprocessors

微处理器设计者能够定期推出新处理器，通过利用底层技术改进和从根本上重新设计处理器，使其性能提高一倍。内部组织。这种趋势正在减弱。通过传统技术和流水线扩展，越来越难以从通用处理器中获得额外的性能。研究人员已经开始重新思考通用处理器的概念，这意味着在单个芯片上有许多不同的处理器，每个处理器都是为单个应用或一类应用量身定制的。这种异构芯片多处理器（HCMP）可以通过利用定制和多样性来提供更高的整体性能和更低的功耗：为特定应用定制处理器以获得更高的性能和更低的功耗，同时提供足够多的不同处理器以广泛覆盖任意应用。HCMP概念具有巨大的潜力，但目前非常不切实际。设计，验证和制造一个处理器需要数百名具有高度专业知识的工程师长达五年的时间来开发。HCMP通过不同处理器设计的数量来增加这种工作量。该项目解决了HCMP研究中这一被忽视的挑战。该项目探索了一种设计、验证和制造任意超标量处理器的新方法，称为FabScalar。关键思想是开发一个预制规范超标量管道阶段库，具有各种尺寸和特征，使任意超标量处理器能够在自然管道阶段级别自动组合。FabScalar是真正hcmp实际开发的第一步。这些hcmp将在各种应用和底层硅之间提供更有效的桥梁。

Microprocessor designers have been able to periodically roll out new processors that double the performance of their predecessors, by leveraging underlying technology improvements and fundamentally redesigning the processor?s internal organization. This trend is abating. It is increasingly difficult to tap additional performance from a general-purpose processor by traditional technology and pipeline scaling. Researchers have begun rethinking the notion of general-purpose processor to mean many different processors on a single chip, each processor tailored to an individual application or a class of applications. Such a Heterogeneous Chip Multiprocessor (HCMP) can deliver higher overall performance with lower power consumption by exploiting customization and diversity: customizing processors to specific applications for higher performance and lower power, meanwhile providing enough different processors to broadly cover arbitrary applications.The HCMP concept has great potential but it is currently very impractical. Designing, verifying, and fabricating just one processor takes hundreds of engineers with highly specialized expertise up to five years to develop. An HCMP multiplies this effort by the number of different processor designs.The project addresses this overlooked challenge of HCMP research. The project explores a new approach to designing, verifying, and fabricating arbitrary superscalar processors, called FabScalar. The key idea is to develop a library of prefabricated canonical superscalar pipeline stages, in a wide variety of dimensions and features, enabling the automatic composition of arbitrary superscalar processors at the natural pipeline stage level. FabScalar is a first step for the practical development of true HCMPs. These HCMPs will provide a more efficient bridge between diverse applications and the underlying silicon.