SHF: Small: AnyCore: A Universal Superscalar Core

未来的微处理器将包含许多处理核心。这一未来提供了独特的机会，通过提供不同的内核类型来提高性能和降低功耗，每种内核类型都针对应用程序内部和跨应用程序的不同指令级行为进行了优化。面对任意的运行时场景，有多少核心类型、每种类型有多少以及每种类型应该是什么样子的问题令人困惑。这是因为(1)指令级行为是无限多样的，而实际上可以包括的核心设计的数量是有限的；(2)并行应用程序倾向于为其统一的任务而倾向于同构的核心。然而，最优的同构多核处理器对于不同的并行应用是不同的，不是静态的；(3)多编程工作负载倾向于使用不同的核来匹配其不同的任务。然而，最佳的异构型多核处理器取决于任务的混合及其到达系统的速率，这些因素随时间而变化；以及(4)即使我们考虑固定的运行时场景，核心设计的最佳配置也取决于延迟、吞吐量和功率偏好。所有这些因素都会随着时间的推移而变化。因此，尽管多核时代使得提供许多核心类型成为可能并且令人向往，但几乎不可能确定每种类型的类型和数量。本项目提出了AnyCore，一个全面可重构的超标量处理核。AnyCore有一个独特而雄心勃勃的目标：它的数百种配置中的每一种，称为“虚拟制造的核心”，都应该实现与明确设计和制造该核心相同的频率、周期水平的性能和功率。由许多复制的AnyCore组成的新型多核体系结构可以配置成任意的异质和同构多核设计，每个设计都具有固定设计的性能和能力。这将实现任意工作负载类型和构成任务中任意指令级行为的最佳延迟、吞吐量和功率目标。这项研究可能会对未来商业处理器的设计过程以及作为快速模拟平台的教育和研究产生重大影响。

Future microprocessors will contain many processing cores. This future presents a unique opportunity to increase performance and decrease power consumption by providing different core types, each optimized for different instruction-level behavior within and across applications. The questions of how many core types, how many of each type, and what should each type look like, are perplexing in the face of arbitrary run-time scenarios. This is because (1) Instruction-level behavior is infinitely diverse whereas the number of core designs that can be practically included is limited; (2) Parallel applications tend to favor homogeneous cores for their uniform tasks. Yet, the optimal homogeneous multi-core processor differs for different parallel applications, which are not static; (3) Multiprogrammed workloads tend to favor heterogeneous cores to match their diverse tasks. Yet, the optimal heterogeneous multi-core processor depends on the mixture of tasks and their arrival rates to the system, factors which vary over time; and (4) Even if we consider a fixed run-time scenario, the optimal configuration of core designs depends on latency, throughput, and power preferences. All of these factors vary over time. Thus, while the multi-core era makes it possible and desirable to provide many core types, it is nearly impossible to determine which ones and how many of each. This project proposes AnyCore, a comprehensively reconfigurable superscalar processing core. AnyCore has a unique and ambitious objective: each one of its hundreds of configurations, called "virtually fabricated cores", should achieve the same frequency, cycle-level performance, and power as explicitly designing and fabricating just that core. A novel multi-core architecture comprised of many replicated AnyCores can be configured into arbitrary heterogeneous and homogeneous multi-core designs, each having the performance and power of a fixed design. This will enable achieving optimal latency, throughput, and power targets for arbitrary workload types and arbitrary instruction-level behavior within their constituent tasks. The research could have potentially significant impact on the design process of future commercial processors, as well as on education and research as a rapid simulation platform.