SHF: Small: AnyCore: A Universal Superscalar Core

SHF：小型：AnyCore：通用超标量核心

• 批准号: 1018517
• 负责人: Eric Rotenberg
• 金额: $ 45万
• 依托单位: North Carolina State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-09-01 至 2016-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1018517&HistoricalAwards=false
• 关键词: SHF; Small; AnyCore; Universal; Superscalar

Future microprocessors will contain many processing cores. This future presents a unique opportunity to increase performance and decrease power consumption by providing different core types, each optimized for different instruction-level behavior within and across applications. The questions of how many core types, how many of each type, and what should each type look like, are perplexing in the face of arbitrary run-time scenarios. This is because (1) Instruction-level behavior is infinitely diverse whereas the number of core designs that can be practically included is limited; (2) Parallel applications tend to favor homogeneous cores for their uniform tasks. Yet, the optimal homogeneous multi-core processor differs for different parallel applications, which are not static; (3) Multiprogrammed workloads tend to favor heterogeneous cores to match their diverse tasks. Yet, the optimal heterogeneous multi-core processor depends on the mixture of tasks and their arrival rates to the system, factors which vary over time; and (4) Even if we consider a fixed run-time scenario, the optimal configuration of core designs depends on latency, throughput, and power preferences. All of these factors vary over time. Thus, while the multi-core era makes it possible and desirable to provide many core types, it is nearly impossible to determine which ones and how many of each. This project proposes AnyCore, a comprehensively reconfigurable superscalar processing core. AnyCore has a unique and ambitious objective: each one of its hundreds of configurations, called "virtually fabricated cores", should achieve the same frequency, cycle-level performance, and power as explicitly designing and fabricating just that core. A novel multi-core architecture comprised of many replicated AnyCores can be configured into arbitrary heterogeneous and homogeneous multi-core designs, each having the performance and power of a fixed design. This will enable achieving optimal latency, throughput, and power targets for arbitrary workload types and arbitrary instruction-level behavior within their constituent tasks. The research could have potentially significant impact on the design process of future commercial processors, as well as on education and research as a rapid simulation platform.

未来的微处理器将包含许多处理核心。这个未来提供了一个独特的机会，通过提供不同的核心类型来提高性能和降低功耗，每个核心类型都针对应用程序内和应用程序之间的不同指令级行为进行了优化。面对任意的运行时场景，有多少个核心类型、每种类型有多少个以及每种类型应该是什么样子的问题是令人困惑的。这是因为（1）指令级行为是无限多样的，而实际上可以包含的核心设计的数量是有限的； (2) 并行应用程序倾向于使用同构核心来执行统一的任务。然而，对于不同的并行应用，最优的同构多核处理器是不同的，它不是一成不变的； (3) 多道程序工作负载倾向于使用异构核心来匹配其不同的任务。然而，最佳的异构多核处理器取决于任务的混合及其到达系统的速率，这些因素会随着时间的推移而变化； (4) 即使我们考虑固定的运行时场景，核心设计的最佳配置也取决于延迟、吞吐量和功耗偏好。所有这些因素都会随着时间的推移而变化。因此，虽然多核时代使得提供多种核心类型成为可能并且是可取的，但几乎不可能确定哪些核心类型以及每种核心类型的数量。该项目提出了 AnyCore，一个全面可重构的超标量处理核心。 AnyCore 有一个独特而雄心勃勃的目标：其数百种配置中的每一种（称为“虚拟制造的核心”）都应实现与明确设计和制造该核心相同的频率、周期级性能和功率。由许多复制的 AnyCore 组成的新颖多核架构可以配置为任意异构和同构多核设计，每个设计都具有固定设计的性能和功能。这将使任意工作负载类型和其组成任务中的任意指令级行为实现最佳延迟、吞吐量和功率目标。该研究可能对未来商用处理器的设计过程以及作为快速仿真平台的教育和研究产生潜在的重大影响。