SHF: Small: Design for Competitive Automated Layout (DCAL) of Mobile Application Processors

SHF：小型：移动应用处理器竞争性自动布局 (DCAL) 设计

• 批准号: 1218608
• 负责人: Eric Rotenberg
• 金额: $ 35万
• 依托单位: North Carolina State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-08-01 至 2017-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1218608&HistoricalAwards=false
• 关键词: SHF; Small; Design; Competitive; Automated

Smart phones, tablet computers, and other mobile devices are transforming the way people work, play, and interact. Their mobility, connection to the cloud, and integration of sensors, computation and communication have inspired unique applications unforeseen just a short time ago. The future holds even greater promise, as applications fuse diverse inputs to deliver new levels of situation awareness and embedded intelligence. To fuel this rapidly growing market, the processors that power mobile devices must be designed more quickly than processors in conventional computers, even as the complexity of mobile processors approaches that of desktop and server processors. Product development is accelerated by licensing hardware descriptions of the latest processors - called soft cores - from third parties, and integrating them with proprietary designs into an overall system-on-chip. Unfortunately, there is an additional step that erodes the productivity gains won by licensing soft cores. A soft core must be converted into a hard core, i.e., a circuit layout that can be fabricated in a semiconductor foundry. Producing a high-quality layout is a painstaking, manual process requiring niche expertise. Alternatively, automated synthesis and place-and-route (SPR) tools can be used, but they produce poor layouts with sub-par performance and power consumption.This research combines the convenience of automated layout with the quality of manual layout. The key innovation is to not compromise on automation - SPR must be used - but rather to modify the design of mobile processors so that SPR is able to produce a quality layout on par with manual layout. That is, the mobile processor is designed with the knowledge that SPR is going to be used. This new paradigm is called Design for Competitive Automated Layout (DCAL). DCAL applies a novel regimen of design strategies at multiple levels that enables SPR to produce competitive layouts. A common theme across all levels is to restructure or eliminate sources of processor complexity that SPR handles poorly. (1) Circuit-level DCAL: Highly-ported memory structures traditionally require intense manual layout. Making matters worse, there are many of them in a modern processor. These are restructured to achieve quality layouts without manual effort. (2) Microarchitecture-level DCAL: The most challenging processor units are restructured so that aggressive circuit and layout optimizations for meeting timing closure are rendered unnecessary. (3) Core-level DCAL: Designing a single microarchitecture that performs well across arbitrary program phases is a significant source of complexity. Core-level DCAL divides program behaviors into useful classes and provides dedicated core designs for these classes; the cores are streamlined for the targeted behaviors, enabling SPR to produce quality physical designs. (4) ISA-level DCAL: For portability across many different processors, mobile device software is often distributed using a virtual instruction-set-architecture (ISA) that does not correspond to any particular processor ISA. The prerequisite for translating the virtual ISA into a processor ISA on-the-fly opens the door to improvising on the processor's ISA for one or multiple core types, with the aim of further streamlining cores for SPR to generate quality physical designs.The economic and societal benefits of DCAL are tangible. Automation accelerates innovation by allowing companies to focus more on developing richer user experiences and less on low-level technology that makes it all possible. Moreover, automation puts this technology into the hands of more people, including folks without niche expertise and small nimble design teams. Both companies and everyday users profit from the fact that more innovative products are being delivered to market sooner.

智能手机、平板电脑和其他移动的设备正在改变人们工作、娱乐和互动的方式。它们的移动性、与云的连接以及传感器、计算和通信的集成激发了不久前无法预见的独特应用。随着应用融合不同的输入，提供新水平的态势感知和嵌入式智能，未来将有更大的希望。为了推动这一快速增长的市场，为移动的设备提供动力的处理器必须比传统计算机中的处理器设计得更快，即使移动的处理器的复杂性接近台式机和服务器处理器。通过从第三方许可最新处理器的硬件描述（称为软核），并将其与专有设计集成到整个片上系统中，加快了产品开发。不幸的是，还有一个额外的步骤会侵蚀通过许可软核所赢得的生产率提高。软核必须转换为硬核，即，一种可在半导体代工厂中制造的电路布局。制作高质量的布局是一个艰苦的手工过程，需要专业知识。另外，自动综合和布局和布线（SPR）工具可以使用，但他们产生的不良布局与低于标准的性能和功耗。本研究结合了自动布局的方便性和手动布局的质量。关键的创新是不妥协的自动化- SPR必须使用-而是修改设计的移动的处理器，使SPR能够产生一个高质量的布局与手动布局。也就是说，移动的处理器被设计为具有将要使用SPR的知识。这种新的范例被称为竞争性自动布局设计（DCAL）。DCAL在多个层次上应用了一种新的设计策略，使SPR能够产生有竞争力的布局。所有级别的一个共同主题是重组或消除SPR处理不佳的处理器复杂性来源。(1)电路级DCAL：高度移植的内存结构传统上需要大量的手动布局。更糟糕的是，在现代处理器中有许多这样的东西。这些都是重新结构，以实现高质量的布局，而无需手动工作。(2)微架构级DCAL：最具挑战性的处理器单元进行了重组，使积极的电路和布局优化，以满足时序收敛是不必要的。(3)核心级DCAL：设计一个在任意程序阶段都能很好执行的微架构是复杂性的重要来源。核心级DCAL将程序行为划分为有用的类，并为这些类提供专用的核心设计;核心针对目标行为进行了精简，使SPR能够产生高质量的物理设计。(4)ISA级DCAL：为了跨许多不同处理器的可移植性，移动终端软件通常使用不对应于任何特定处理器伊萨的虚拟配置集架构（伊萨）来分发。将虚拟伊萨动态转换为处理器ISA的先决条件为针对一个或多个核心类型即兴创作处理器伊萨打开了大门，目的是进一步简化SPR的核心，以生成高质量的物理设计。DCAL的经济和社会效益是有形的。自动化加速了创新，使公司能够更多地专注于开发更丰富的用户体验，而不是使这一切成为可能的低级技术。此外，自动化将这项技术交给了更多的人，包括没有利基专业知识的人和小型灵活的设计团队。公司和日常用户都受益于更多创新产品更快地推向市场。