Integration of Magnetic Tunnel Junctions with Quantum Negative Differential Resistance Devices

提出的研究旨在单片集成硅纳米电子学与自旋电子学。将研究双势垒磁隧道结（MTJ）与CMOS兼容的硅基量子谐振隧道二极管（RTD）的垂直集成。通过物理模型和仿真表明，MTJ和RTD的一系列组合可以显着提高隧道磁电阻（TMR）比，这是超高密度存储器应用所需要的。利用不同矫顽力的铁磁层，双势垒MTJ可以有四个不同的电阻值，代表信息存储的四种状态。RTD的负差分电阻（NDR）特性用于读取mtj的状态，以及在不造成面积损失的情况下增加TMR比。该提案将建立在提案团队成功集成硅基共振带间隧道二极管（RITD）与CMOS的经验之上。该装置由夹在两个不同极性掺杂区域之间的Sage间隔层组成，全部通过低温分子束蜂房生长。基本的双势垒磁隧道结结构将由Ta 5 nm/Ni79Fe21 3 nm/Cu 20 nm/Ni79Fe21 3 nm/Ir22Mn78 10 nm/Co75Fe25 4 nm/Al 0.8 nm-oxide/ Ni79Fe21 3 nm/Al 0.8 nm-oxide/ Co75Fe25 4 nm/ Ta 5 nm组成。将进行详细的研究项目，以调查加工限制，如布局，清洁过程，热预算和模式的过程中提出的整合。此外，还将建立理论模型来预测MTJ-RITD结构的响应。这将是RIT、海军研究实验室和位于纽约普莱恩维尤的Veeco之间的合作成果。RIT将进行CMOS-RITD-MTJ芯片设计，掩模制造，工艺开发，制造，建模和电气测试。NRL将为RITD结构提供MBE生长，Veeco将提供MTJ薄膜沉积。本研究的新颖之处在于，它由一组异质的、广泛传播的不同技术组成，集成在硅CMOS兼容平台上，有可能发展成逻辑存储应用的新架构。此外，该技术在新的信息处理中利用了三种不同的状态变量：电荷、自旋取向和量子态。通过这些功能的融合，MTJ/RITD MRAM技术有望在单元尺寸方面优于当前最先进的1T-1MTJ MRAM架构，因为垂直集成方法，高信噪比，因为MR比增强，易于制造和成本。磁电子学与传统电子学的共存将开辟新的领域。PI和Co-PI在使用CMOS芯片进行RITD制造以及与NRL和Veeco的协同合作方面拥有丰富的经验。更广泛的影响纳米技术和电子学的交叉将在未来几十年产生许多新的创新。预计各种技术与标准硅技术的融合将对存储器和显示以及随后的逻辑产生巨大影响。所提出的研究是针对电子的发展。多值存储器等自旋电子系统将提供超高密度存储器，这对于未来的信息需求以及在全球竞争时代保持美国工业的创新优势至关重要。该研究将涉及教师和学生与国家实验室（NRL）和行业（Veeco）的参与。PI和Co-PI将开发新的课程——“自旋电子学基础”和“新型存储技术”，以丰富工程教育。这些课程也将为工业界和学术界提供远程授课。该计划将通过K-12合作伙伴关系，吸引社区大学和代表性不足的学生群体学习科学和工程，促进社区的科学和工程。

The proposed study seeks to monolithically integrate silicon nanoelectronics with spintronics. Vertical integration of double barrier magnetic tunnel junctions (MTJ) will be investigated with CMOS compatible silicon based quantum resonant tunnel diodes (RTD). It has been shown through physical models and simulations that a series combination of MTJ and RTD could increase the tunneling magnetoresistance (TMR) ratio significantly, which is desirable for ultra high-density memory applications. Utilizing ferromagnetic layers of different coercivities, the double barrier MTJ can have four distinct resistance values, representing four states in which the information is stored. The negative differential resistance (NDR) characteristic of the RTD is used to read the state of the MTJs, as well as to increases the TMR ratio without area penalty. The proposal will build upon the experience of the proposing team in successful integration of Si based Resonant Interband Tunnel Diodes (RITD) with CMOS. This device consists of Sage spacer layer sandwiched between two delta-doped regions of different polarities, all grown via low temperature molecular beam apiary. The basic double barrier magnetic tunnel junction structure will consist of Ta 5 nm/Ni79Fe21 3 nm/Cu 20 nm/Ni79Fe21 3 nm/Ir22Mn78 10 nm/Co75Fe25 4 nm/Al 0.8 nm-oxide/ Ni79Fe21 3 nm / Al 0.8 nm-oxide /Co75Fe25 4 nm/ /Ta 5 nm. A detailed research project will be undertaken to investigate processing constraints such as layout, clean processes, thermal budget and patterning process for the proposed integration. In addition, theoretical models will be developed to predict the response of the MTJ-RITD structures. This will be a collaborative effort between RIT, Naval Research Laboratory and Veeco located at Plainview, New York. RIT will carryout CMOS-RITD-MTJ chip design, mask fabrication, process development, fabrication, modeling and electrical test. NRL will provide MBE growth for RITD structures and Veeco will provide MTJ films depositions. Intellectual Merit The novelty of this proposed research lies in the fact that it consists of a heterogeneous set of novel and widely spread disparate technologies integrated on silicon CMOS compatible platform that has a potential to develop into new architectures for logic-memory applications. In addition, the proposed technology utilizes three different state variables in the novel information processing: electric charge, spin orientation, and quantum state. By the convergence of these functionalities, the MTJ/RITD MRAM technology is expected to outperform the current state-of-the-art 1T-1MTJ MRAM architecture in term of cell size due to the vertical integration approach, high signal-to-noise ratio due to MR ratio enhancement, and ease of fabrication and cost. The coexistence of magnetoelectronics with conventional electronics will open new frontiers. The PI, and Co-PI have extensive experience in RITD fabrication with CMOS chips and synergistic collaborations with NRL and Veeco. Broader Impact The intersection of nanotechnology and electronics will yield many new innovations over the coming decades. It is anticipated that convergence of various technologies with the standard silicon technology has the potential for tremendous impact in memories and displays and subsequently in logic. The proposed research is aimed at the development of electronic.spintronic systems such as multi-value memory that will provide ultra high density memory, extremely important for the information demands of the future and for maintaining innovative edge of the US industry in the era of global competition. The study will involve participation of faculty and students with a national laboratory (NRL) and industry (Veeco). The PI and Co-PI will develop new courses- "Fundamentals of Spintronics" and "Novel Memory Technologies" that will enrich engineering education. These courses will also be made available for distance delivery for industry and academia. The program will promote science and engineering in the community through K-12 partnerships and in attracting community college and underrepresented student groups to science and engineering.