Integration of Magnetic Tunnel Junctions with Quantum Negative Differential Resistance Devices

磁隧道结与量子负微分电阻器件的集成

• 批准号: 0501460
• 负责人: Santosh Kurinec
• 金额: --
• 依托单位: Rochester Institute of Tech
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2005
• 资助国家: 美国
• 起止时间: 2005-05-01 至 2009-04-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0501460&HistoricalAwards=false
• 关键词: Integration; Magnetic; Tunnel; Junctions; Quantum

The proposed study seeks to monolithically integrate silicon nanoelectronics with spintronics. Vertical integration of double barrier magnetic tunnel junctions (MTJ) will be investigated with CMOS compatible silicon based quantum resonant tunnel diodes (RTD). It has been shown through physical models and simulations that a series combination of MTJ and RTD could increase the tunneling magnetoresistance (TMR) ratio significantly, which is desirable for ultra high-density memory applications. Utilizing ferromagnetic layers of different coercivities, the double barrier MTJ can have four distinct resistance values, representing four states in which the information is stored. The negative differential resistance (NDR) characteristic of the RTD is used to read the state of the MTJs, as well as to increases the TMR ratio without area penalty. The proposal will build upon the experience of the proposing team in successful integration of Si based Resonant Interband Tunnel Diodes (RITD) with CMOS. This device consists of Sage spacer layer sandwiched between two delta-doped regions of different polarities, all grown via low temperature molecular beam apiary. The basic double barrier magnetic tunnel junction structure will consist of Ta 5 nm/Ni79Fe21 3 nm/Cu 20 nm/Ni79Fe21 3 nm/Ir22Mn78 10 nm/Co75Fe25 4 nm/Al 0.8 nm-oxide/ Ni79Fe21 3 nm / Al 0.8 nm-oxide /Co75Fe25 4 nm/ /Ta 5 nm. A detailed research project will be undertaken to investigate processing constraints such as layout, clean processes, thermal budget and patterning process for the proposed integration. In addition, theoretical models will be developed to predict the response of the MTJ-RITD structures. This will be a collaborative effort between RIT, Naval Research Laboratory and Veeco located at Plainview, New York. RIT will carryout CMOS-RITD-MTJ chip design, mask fabrication, process development, fabrication, modeling and electrical test. NRL will provide MBE growth for RITD structures and Veeco will provide MTJ films depositions. Intellectual Merit The novelty of this proposed research lies in the fact that it consists of a heterogeneous set of novel and widely spread disparate technologies integrated on silicon CMOS compatible platform that has a potential to develop into new architectures for logic-memory applications. In addition, the proposed technology utilizes three different state variables in the novel information processing: electric charge, spin orientation, and quantum state. By the convergence of these functionalities, the MTJ/RITD MRAM technology is expected to outperform the current state-of-the-art 1T-1MTJ MRAM architecture in term of cell size due to the vertical integration approach, high signal-to-noise ratio due to MR ratio enhancement, and ease of fabrication and cost. The coexistence of magnetoelectronics with conventional electronics will open new frontiers. The PI, and Co-PI have extensive experience in RITD fabrication with CMOS chips and synergistic collaborations with NRL and Veeco. Broader Impact The intersection of nanotechnology and electronics will yield many new innovations over the coming decades. It is anticipated that convergence of various technologies with the standard silicon technology has the potential for tremendous impact in memories and displays and subsequently in logic. The proposed research is aimed at the development of electronic.spintronic systems such as multi-value memory that will provide ultra high density memory, extremely important for the information demands of the future and for maintaining innovative edge of the US industry in the era of global competition. The study will involve participation of faculty and students with a national laboratory (NRL) and industry (Veeco). The PI and Co-PI will develop new courses- "Fundamentals of Spintronics" and "Novel Memory Technologies" that will enrich engineering education. These courses will also be made available for distance delivery for industry and academia. The program will promote science and engineering in the community through K-12 partnerships and in attracting community college and underrepresented student groups to science and engineering.

这项研究旨在将硅纳米电子学与自旋电子学单片集成。 本论文将探讨以互补式金氧半导体（CMOS）相容的矽基量子共振隧穿二极体（RTD）来实现双阻障磁性隧道接面（MTJ）的垂直整合。 通过物理模型和模拟已经表明，MTJ和RTD的串联组合可以显著增加隧穿磁阻（TMR）比，这对于超高密度存储器应用是期望的。 利用不同介电率的铁磁层，双势垒MTJ可以具有四个不同的电阻值，表示存储信息的四种状态。 RTD的负微分电阻（NDR）特性用于读取MTJ的状态，以及增加TMR比而不增加面积损失。 该提案将建立在提案团队成功集成硅基谐振带间隧道二极管（RITD）与CMOS的经验之上。 该器件由Sage间隔层夹在两个不同极性的δ掺杂区域之间组成，所有区域都通过低温分子束生长。 基本的双势垒磁性隧道结结构 将由Ta 5 nm/Ni 79 Fe 21 3 nm/Cu 20 nm/Ni 79 Fe 21 3 nm/Ir 22 Mn 78 10 nm/Co 75 Fe 25 4 nm/Al 0.8 nm-氧化物/Ni 79 Fe 21 3 nm / Al 0.8 nm-氧化物/Co 75 Fe 25 4 nm/ /Ta 5 nm组成。 一个详细的研究项目将进行调查的工艺约束，如布局，清洁工艺，热预算和图案化过程中提出的集成。 此外，将开发理论模型来预测MTJ-RITD结构的响应。 这将是RIT、海军研究实验室和位于纽约普莱恩维尤的Veeco之间的合作努力。 RIT将进行CMOS-RITD-MTJ芯片设计，掩模制造，工艺开发，制造，建模和电气测试。NRL将为RITD结构提供MBE生长，Veeco将提供MTJ薄膜沉积。 智力优点-这项研究的新奇在于，它包括一个异构的一套新颖的和广泛传播的不同的技术集成在硅CMOS兼容平台，有可能发展成新的架构的逻辑存储器应用。 此外，该技术在新的信息处理中利用了三种不同的状态变量：电荷、自旋取向和量子态。通过这些功能的融合，预期MTJ/RITD MRAM技术在由于垂直集成方法而导致的单元尺寸、由于MR比增强而导致的高信噪比以及易于制造和成本方面优于当前最先进的1 T-1 MTJ MRAM架构。 磁电子学与传统电子学的共存将开辟新的领域。PI和Co-PI在使用CMOS芯片制造RITD以及与NRL和Veeco的协同合作方面拥有丰富的经验。 纳米技术和电子学的交叉将在未来几十年产生许多新的创新。预计各种技术与标准硅技术的融合有可能对存储器和显示器以及随后的逻辑产生巨大影响。该研究旨在开发电子自旋电子系统，如多值存储器，它将提供超高密度存储器，这对未来的信息需求和在全球竞争时代保持美国工业的创新优势至关重要。该研究将涉及教师和学生与国家实验室（NRL）和行业（Veeco）的参与。 PI和Co-PI将开发新的课程-“自旋电子学基础”和“新型存储技术”，这将丰富工程教育。 这些课程也将提供给工业界和学术界远程授课。 该计划将通过K-12合作伙伴关系促进社区的科学和工程，并吸引社区学院和代表性不足的学生团体参加科学和工程。