CAREER: Power-Performance Considerations of Thread-level Parallelism in On-chip Multicore Architectures

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As the microprocessor industry moves toward multicore solutions (several processor cores on a single chip), performance growth on these inherently power-constrained platforms will increasingly rely upon their ability to support thread-level parallelism efficiently. The goal of the research project in this CAREER proposal is to develop the necessary insights for the successful design of mechanisms that can address the unique power-performance opportunities and challenges of running parallel applications on multicore chip architectures. We explore power-aware control of parallelism in such architectures by combining information about the application's parallel behavior, the operating constraints, and the chip's support for voltage/frequency scaling and other mechanisms for power management. Integral to this CAREER proposal is a broad educational plan with specific goals at several education levels. We also provide concrete initiatives to promote engineering among high-school girls and underrepresented minorities, and to mentor them throughout their college years.