CAREER: Power-Performance Considerations of Thread-level Parallelism in On-chip Multicore Architectures

随着微处理器行业转向多核解决方案(单个芯片上的多个处理器核心)，这些固有的功率受限平台上的性能增长将越来越依赖于它们高效支持线程级并行的能力。这份职业提案中研究项目的目标是为成功设计能够解决在多核芯片架构上运行并行应用程序的独特功率性能机会和挑战的机制开发必要的洞察力。通过结合有关应用程序的并行行为、操作限制、芯片对电压/频率调节的支持以及其他电源管理机制的信息，我们探索了此类架构中的并行性的功耗感知控制。这份职业计划的组成部分是一个广泛的教育计划，在几个教育级别上有具体的目标。我们还提供具体倡议，在高中女生和代表性不足的少数族裔中推广工程学，并在她们的整个大学生涯中指导她们。

As the microprocessor industry moves toward multicore solutions (several processor cores on a single chip), performance growth on these inherently power-constrained platforms will increasingly rely upon their ability to support thread-level parallelism efficiently. The goal of the research project in this CAREER proposal is to develop the necessary insights for the successful design of mechanisms that can address the unique power-performance opportunities and challenges of running parallel applications on multicore chip architectures. We explore power-aware control of parallelism in such architectures by combining information about the application's parallel behavior, the operating constraints, and the chip's support for voltage/frequency scaling and other mechanisms for power management. Integral to this CAREER proposal is a broad educational plan with specific goals at several education levels. We also provide concrete initiatives to promote engineering among high-school girls and underrepresented minorities, and to mentor them throughout their college years.