Checkpointed Processor Architectures

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Checkpointed Processor ArchitecturesAbstractThe project proposes Checkpointed Processor Architectures (CPA), a hybrid mode of execution based on a combination of traditional in-order commit support and selective state checkpointing. CPA decouples resource recycling from instruction commit permitting more aggressive reclamation and higher utilization. It also performs speculative commit of some long-latency memory operations, allowing subsequent instructions to complete and commit. To recover from corrupted states due to aggressive speculation, CPA processors rely on their checkpointed state. The project will explore the integration of CPA in processors with support for simultaneous multithreading, and with chip multiprocessors. The project will also investigate the synergy between CPA and thread-level speculation, an upcoming technology that bridges the gap between sequential and parallel computing.CPA's departure from traditional instruction processing will allow processors to deliver higher performance growth without oversizing critical resources, which affects the clock rate adversely. As a result, CPA will help overcome the performance stagnation in evolutionary processor architectures. Furthermore, our integrative approach with emerging parallel and speculatively parallel architectures will ensure a broad and lasting impact. Finally, the insights developed in the CPA mechanisms and interactions will help better understand the co-design aspects of microprocessor and parallel architectures, in the lab and in the classroom.