Checkpointed Processor Architectures

检查点处理器架构

• 批准号: 0429922
• 负责人: Jose Martinez
• 金额: --
• 依托单位: Cornell University
• 依托单位国家: 美国
• 项目类别: Continuing grant
• 财政年份: 2004
• 资助国家: 美国
• 起止时间: 2004-09-15 至 2007-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0429922&HistoricalAwards=false
• 关键词: Checkpointed; Processor; Architectures

Checkpointed Processor ArchitecturesAbstractThe project proposes Checkpointed Processor Architectures (CPA), a hybrid mode of execution based on a combination of traditional in-order commit support and selective state checkpointing. CPA decouples resource recycling from instruction commit permitting more aggressive reclamation and higher utilization. It also performs speculative commit of some long-latency memory operations, allowing subsequent instructions to complete and commit. To recover from corrupted states due to aggressive speculation, CPA processors rely on their checkpointed state. The project will explore the integration of CPA in processors with support for simultaneous multithreading, and with chip multiprocessors. The project will also investigate the synergy between CPA and thread-level speculation, an upcoming technology that bridges the gap between sequential and parallel computing.CPA's departure from traditional instruction processing will allow processors to deliver higher performance growth without oversizing critical resources, which affects the clock rate adversely. As a result, CPA will help overcome the performance stagnation in evolutionary processor architectures. Furthermore, our integrative approach with emerging parallel and speculatively parallel architectures will ensure a broad and lasting impact. Finally, the insights developed in the CPA mechanisms and interactions will help better understand the co-design aspects of microprocessor and parallel architectures, in the lab and in the classroom.

检查点处理器体系结构摘要该项目提出了检查点处理器体系结构（CPA），一种基于传统的有序提交支持和选择性状态检查点相结合的混合执行模式。 CPA从指令提交开始进行资源回收，允许更积极的回收和更高的利用率。 它还执行一些长延迟内存操作的推测性提交，允许后续指令完成和提交。 为了从由于攻击性推测而导致的损坏状态中恢复，CPA处理器依赖于它们的检查点状态。 该项目将探索CPA在处理器中的集成，支持同时多线程，并与芯片多处理器。 该项目还将研究CPA和线程级推测之间的协同作用，线程级推测是一种即将到来的技术，它弥合了顺序计算和并行计算之间的差距。CPA与传统指令处理的背离将使处理器能够提供更高的性能增长，而不会使关键资源过大，从而对时钟速率产生不利影响。 因此，CPA将有助于克服进化处理器架构中的性能停滞。 此外，我们的综合方法与新兴的并行和推测并行架构将确保广泛和持久的影响。 最后，在CPA机制和交互中开发的见解将有助于更好地理解微处理器和并行架构的协同设计方面，在实验室和课堂上。