Modeling and simulation of transport and trapping phenomena in high-k-dielectrics

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Continuing the miniaturization of integrated circuits inevitably requires the replacement of SiO2 by other insulators with superior dielectric properties, the so called ‘high-κ’ dielectrics (κ: permittivity). Introduction of high-κs solves the most urgent problem of semiconductor industry, exponentially growing leakage currents, and thus enables further scaling.These novel materials are mostly not well researched, especially electronic transport is not yet understood. We aim at developing physical models describing the transport processes and transport-related phenomena (e.g. charge trapping, degradation). These models will subsequently be embedded in a kinetic Monte Carlo algorithm and incorporated into simulation tools. State-of-the-art zirconium-based dielectrics, now employed in the newest generation of processors and memory chips will be investigated by extensive comparison of simulations with experimental data to put the models to the test. Detailed sensitivity analysis of high-κ structures on experimentally hard to access parameters (e.g. interface roughness, defect density and distribution) will be carried out.The proposed theoretical activity is intended to provide backup to the characterization and fabrication activities carried out worldwide. Emphasis will be laid on the identification of scaling potentials and possible problem areas at an early stage of material development.