Architectural Support for Parallelism on Multi-Core Architectures

多核架构上并行性的架构支持

• 批准号: 0702349
• 负责人: Dean Tullsen
• 金额: $ 30万
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-07-01 至 2010-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0702349&HistoricalAwards=false
• 关键词: Architectural; Support; Parallelism; Multi; Core

Industry is shifting from uniprocessor-oriented processors to architectures which execute multiple threads on a single chip. This includes multithreaded and, increasingly, multiple-core processors. That is, increases in transistor count and density are no longer being applied to increased single-cpu or single-thread performance. Instead, those transistors are being used to increase the number of available execution contexts. The most significant impact of this technology shift is that microprocessors will only continue to scale in performance in the presence of abundant thread level parallelism.For many workloads, the parallelism available will quickly fall short of the parallelism the hardware is able to exploit. The performance advances of future processor generations then become unavailable in those environments. This parallelism gap is inevitable, because there is no clear limit in sight to how many contexts we can place on a chip.This research will create a toolchest of solutions to enable the effective use of on-chip parallelism to improve performance, power efficiency, and correctness of programs. Particular emphasis is on applications for which traditional methods of parallelism have been ineffective. This research will focus on solutions in the following areas. More efficient parallel architectures enable better exploitation of available parallelism by ensuring that what does run in parallel does so as effectively as possible. Non-traditional forms of parallelism allow multiple contexts to provide speedup, without necessarily departing from the single execution stream model. Dynamically-generated parallelism will use lightweight hardware monitors to identify code that is potentially memory-independent, and separate threads will analyze and possibly rewrite the code to exploit the parallelism dynamically. In addition to providing performance, multi-core architectures can be exploited to provide new functionality that either is not possible, or not performance-effective, on a single core. This functionality includes software fault tolerance, debugging, and security.

工业正在从面向单处理器的处理器转向在单个芯片上执行多线程的体系结构。这包括多线程处理器以及越来越多的多核处理器。也就是说，晶体管数量和密度的增加不再适用于单CPU或单线程性能的提高。相反，这些晶体管正被用来增加可用执行上下文的数量。这种技术转变最显著的影响是，只有在存在大量的线程级并行的情况下，微处理器才会继续在性能上进行扩展。对于许多工作负载，可用的并行度将很快低于硬件能够利用的并行度。因此，未来几代处理器的性能改进在这些环境中将变得不可用。这种并行性差距是不可避免的，因为我们在一个芯片上可以放置多少上下文目前还没有明确的限制。这项研究将创建一个解决方案的工具箱，以使芯片上的并行性能够有效地使用，以提高程序的性能、功率效率和正确性。特别强调的是传统的并行方法已经无效的应用程序。本研究将侧重于以下几个方面的解决方案。更高效的并行体系结构通过确保并行运行的内容尽可能有效地实现对可用并行性的更好利用。非传统形式的并行性允许多个上下文提供加速，而不必背离单一执行流模型。动态生成的并行性将使用轻量级硬件监视器来识别可能与内存无关的代码，单独的线程将分析并可能重写代码以动态利用并行性。除了提供性能外，还可以利用多核体系结构来提供在单核上无法实现或性能效率不高的新功能。此功能包括软件容错、调试和安全性。