Improving Memory Power and Performance for Multicore Processors

提高多核处理器的内存功率和性能

• 批准号: 0702799
• 负责人: John Carter
• 金额: $ 30万
• 依托单位: University of Utah
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-06-01 至 2010-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0702799&HistoricalAwards=false
• 关键词: Improving; Memory; Power; Performance; Multicore

Future microprocessors will be multicore systems with significant real estate dedicated to on-chip cache memory. The potential performance of multicore processors far exceed that of traditional single-core processors, but their performance is limited by the memory system''s inability to deliver data to cores in a timely fashion. Traditional techniques for overcoming this memory bottleneck problem are power hungry, which makes them unsuitable for future power-limited designs. To overcome the memory bottleneck problem, we are evaluating a wide variety of multicore memory hierarchy design space options, with an eye towards both improving performance and decreasing power. Among the design options we are investigating are hierarchical versus tiled cache architectures, support for dynamic tile allocation policies, support for moving select computation to data, support for vector-style gather-scatter operations, support for selective updates, power-aware coherence protocols and prefetching mechanisms, and coherence and prefetching mechanisms that exploit heterogeneous wire technologies. Preliminary results indicate that these mechanisms will significantly increase performance and reduce power dissipation in future multicore processors.

未来的微处理器将是具有专用于片上高速缓冲存储器的显著真实的资产的多核系统。 多核处理器的潜在性能远远超过传统的单核处理器，但它们的性能受到内存系统无法及时将数据传递到内核的限制。传统的技术，以克服这一内存瓶颈问题是耗电，这使得他们不适合未来的功率有限的设计。 为了克服内存瓶颈问题，我们正在评估各种各样的多核内存层次设计空间选项，着眼于提高性能和降低功耗。 我们正在研究的设计选项包括分层与分片缓存架构，支持动态分片分配策略，支持将选择计算移动到数据，支持矢量风格的分散操作，支持选择性更新，功率感知一致性协议和预取机制，以及利用异构线技术的一致性和预取机制。 初步结果表明，这些机制将显着提高性能，降低功耗，在未来的多核处理器。