Improving Memory Power and Performance for Multicore Processors

未来的微处理器将是具有大量空间的多核系统，专门用于片上高速缓存存储器。多核处理器的潜在性能远远超过传统单核处理器，但其性能受到存储系统S无法及时向内核传递数据的限制。克服这一内存瓶颈问题的传统技术需要耗电，这使得它们不适合未来的功率受限设计。为了克服内存瓶颈问题，我们正在评估各种多核内存层次结构设计空间选项，着眼于提高性能和降低功耗。我们正在研究的设计选项包括分层与平铺缓存体系结构、对动态平铺分配策略的支持、对将选择计算移动到数据的支持、对向量式聚集-分散操作的支持、对选择性更新的支持、对功率感知的一致性协议和预取机制的支持、以及利用异构线技术的一致性和预取机制。初步结果表明，在未来的多核处理器中，这些机制将显著提高性能并降低功耗。

Future microprocessors will be multicore systems with significant real estate dedicated to on-chip cache memory. The potential performance of multicore processors far exceed that of traditional single-core processors, but their performance is limited by the memory system''s inability to deliver data to cores in a timely fashion. Traditional techniques for overcoming this memory bottleneck problem are power hungry, which makes them unsuitable for future power-limited designs. To overcome the memory bottleneck problem, we are evaluating a wide variety of multicore memory hierarchy design space options, with an eye towards both improving performance and decreasing power. Among the design options we are investigating are hierarchical versus tiled cache architectures, support for dynamic tile allocation policies, support for moving select computation to data, support for vector-style gather-scatter operations, support for selective updates, power-aware coherence protocols and prefetching mechanisms, and coherence and prefetching mechanisms that exploit heterogeneous wire technologies. Preliminary results indicate that these mechanisms will significantly increase performance and reduce power dissipation in future multicore processors.