PERICES-3: Providing Efficient Reliability in Critical Embedded Systems (Phase 3)

PERICES-3：在关键嵌入式系统中提供高效的可靠性（第 3 阶段）

• 批准号: 182021842
• 负责人: Professor Mehdi B. Tahoori, Ph.D.
• 金额: --
• 依托单位: Institut für Technische Informatik
• 依托单位国家: 德国
• 项目类别: Priority Programmes
• 财政年份: 2010
• 资助国家: 德国
• 起止时间: 2009-12-31 至 2017-12-31
• 项目状态: 已结题
• 来源: https://gepris.dfg.de/gepris/projekt/182021842?language=en
• 关键词: PERICES; Providing; Efficient; Reliability; Critical

Improvements in chip manufacturing technology have propelled an astonishing growth of embedded systems which are integrated into our daily lives. However, this trend is facing serious challenges, both at device and system levels. As the minimum feature size continues to shrink, a host of vulnerabilities, such as radiation-induced soft errors and intermittent errors from weak cells and process variations, will influence the robustness, reliability, and availability of embedded and critical systems. The traditional design paradigm assumes no failure during the lifetime a design. Even classical fault tolerant approaches, such as duplication or Triple Modular Redundancy (TMR), which are used for high-end mainframes and safety-critical applications, are very costly and effective only for very small defect rates, and therefore not applicable to embedded systems. In this project we will develop techniques and methodologies to ensure robustness, reliability, availability, and recoverability of critical embedded systems at both the hardware and the software levels in a very cost-effective way. We will design a set of techniques and tools for fast and accurate reliability modeling and estimation at various abstraction levels. We will propose concurrent error detection and localization methods (hardware-level) to ensure data integrity. We will also develop novel recovery mechanisms that provide error localization from the design level, and carefully consider how these interact with both the microarchitectural and architectural levels (software-level).

芯片制造技术的进步推动了嵌入式系统的惊人增长，这些系统已融入我们的日常生活。然而，这一趋势在设备和系统层面都面临着严峻的挑战。随着最小特征尺寸的不断缩小，许多漏洞，如辐射引起的软错误和来自弱单元和工艺变化的间歇性错误，将影响嵌入式和关键系统的鲁棒性，可靠性和可用性。传统的设计范式假设在设计的生命周期中没有失败。即使是经典的容错方法，如用于高端大型机和安全关键型应用的复制或三重模块冗余（TMR），也非常昂贵，并且仅对非常小的缺陷率有效，因此不适用于嵌入式系统。在这个项目中，我们将开发技术和方法，以确保在硬件和软件级别的关键嵌入式系统的鲁棒性，可靠性，可用性和可恢复性，在一个非常具有成本效益的方式。我们将设计一套技术和工具，用于在各种抽象级别上快速准确地进行可靠性建模和估计。我们将提出并发错误检测和定位方法（硬件级），以确保数据的完整性。我们还将开发新的恢复机制，从设计层面提供错误定位，并仔细考虑这些如何与微架构和架构层面（软件层面）的互动。