CSR---SMA: Characterizing, Modeling and Mitigating Soft Error Vulnerability in Multithreaded and Multi-core Execution Environments

未来的微处理器将由数十亿个纳米级晶体管组成，这些晶体管被组织成多核多线程微架构。由于纳米尺寸的晶体管对外部事件和制造可变性敏感，因此在数十亿个晶体管中的一个中发生一个或多个故障并影响许多线程中的一个的概率不可忽略。高数据完整性和可用性要求使得可靠性对于计算机来说与性能、功耗和产量一样重要。该项目研究用于表征和数学建模系统级组件（即在微体系结构，操作系统和程序级）对软错误的脆弱性的技术。今天的设计方法优化多核和/或多线程体系结构的性能和功率，但在很大程度上忽略了存在软错误时的可靠性。一个重要而紧迫的研究任务是开发框架，模型和技术来表征和估计软错误的有害影响。本研究通过以下方法解决上述问题：1）开发一个统一的、可靠性感知的仿真框架，以量化由各种异构硬件和软件组件组成的多线程和多核系统的微体系结构软错误脆弱性; 2）建立快速准确的分析模型，以估计和预测软-硬件和软件组件的错误漏洞，而无需使用冗长和详细的模拟;可以定量研究软错误漏洞的框架将使可靠性感知的设计和研究新兴的错误多线程和多核心架构PI将使用这个研究项目的概念，工具，技术和其他成果，向研究生和本科生介绍软错误的性质及其对执行环境的影响。这些教学活动将改进计算机结构、容错计算和纳米计算课程。在这个项目中开发的工具是可访问的，并可通过Web使用，使用由PI实验室开发的设备和中间件。这使得其他学者和工程师可以直接在自己的工作中使用它们。

Future microprocessors will consist of billions of nanoscale transistors organized as multi-core multithreaded microarchitectures. Since nano-sized transistors are sensitive to external events and manufacturing variabilities, there is a non-negligible probability of one or more faults occurring in one of billions of transistors and affecting one of many threads. High data-integrity and availability requirements make reliability as important for computers as performance, power consumption, and yield. This project studies techniques for characterizing and mathematically modeling the vulnerability of system-level components (i.e. at the microarchitecture, OS and program levels) to soft-errors.Today's design methodologies optimize the performance and power of multi-core and/or multithreaded architectures, but largely ignore reliability in the presence of soft errors. An important and urgent research task is to develop frameworks, models and techniques to characterize and estimate the deleterious impact of soft errors. This research addresses the above challenge by 1) developing a unified, reliability-aware simulation framework to quantify microarchitecture soft-error vulnerability of simultaneous-multithreading and multi-core systems consisting of a wide range of heterogeneous hardware and software components; and 2) creating fast and accurate analytical models to estimate and forecast soft-error vulnerabilities of hardware and software components without using lengthy and detailed simulations; Frameworks that can quantitatively study soft error vulnerability will enable reliability-aware designs and research for emerging simultaneous-multithreading and multi-core architectures. The PIs will use the concepts, tools, techniques and other results of this research project to introduce graduate and undergraduate students to the nature of soft errors and their impact on execution environments. These teaching activities will lead to improvements in courses on computer architecture, fault-tolerant computing and nanocomputing. The tools developed in this project are accessible and usable over the Web, using equipment and middleware developed by the PIs laboratory. This makes it straightforward for other academics and engineers to use them in their own work.