Towards A Theory of Communication With Sloppy Analog-to-Digital Conversion: A Framework for Low-Cost Gigabit wireless

蜂窝和WiFi网络的规模经济通过无线通信收发器中的复杂数字信号处理（DSP）算法的低成本集成电路实现来实现。 这种方法中的一个隐含假设是，模拟接收信号可以转换为相当忠实的数字表示，随着链路速度增加到高精度模数转换（ADC）变得过于昂贵和耗电的程度，这个假设就会崩溃。 该项目涉及后一种无线网络的设计：目标是设计以多千兆位速度运行的低成本链路（即，比WiFi快一个数量级以上），利用3-10 GHz频带和60 GHz频带中的大片未许可频谱。 该研究重新考虑了通信收发器的设计，首先假设高速ADC是“草率的”。这项研究涉及使用信息论获得基本的性能基准，并设计实现这些性能基准的DSP算法。最终目标是实现家庭和企业无线网络速度的飞跃，同时保持与低成本硅实现相关的规模经济。传统系统使用6-12位ADC精度，本研究考虑低分辨率通信系统的设计（1-4位）ADC，包括香农理论基准和同步和均衡算法。 由于高速数模转换比ADC更容易，因此研究了将复杂性转移到发射机的预编码策略。 对于正交载波和多载波系统，都考虑使用时间交错ADC来获得更高的精度，从而获得更高的动态范围。 该方法是设计接收器算法，共同解决组件ADC和通道色散之间的失配。

The economies of scale of cellular and WiFi networks are enabled by low-cost integrated circuit implementations of sophisticated digital signal processing (DSP) algorithms in wireless communication transceivers. An implicit assumption in this approach is that analog received signals can be converted to a reasonably faithful digital representation, an assumption that breaks down as link speeds increase to the point that high-precision analog-to-digital conversion (ADC) becomes too costly and power-hungry. This project involves the design of wireless networks in the latter regime: the goal is to design low-cost links operating at multiGigabit speeds (i.e., more than an order of magnitude faster than WiFi), exploiting large swaths of unlicensed spectrum in the 3-10 GHz band and the 60 GHz band. The research rethinks communication transceiver design, with the starting assumption that high-speed ADCs are ``sloppy.'' The research involves obtaining fundamental performance benchmarks using information theory, and devising DSP algorithms that achieve these performance benchmarks. The ultimate objective is to enable a quantum leap in the speed of wireless networks for the home and enterprise, while preserving the economies of scale associated with low-cost silicon implementations.While conventional systems use 6-12 bits of ADC precision, this research considers the design of communication systems for low-resolution (1-4 bits) ADC, including Shannon theoretic benchmarks and algorithms for synchronization and equalization. Since high-speed digital-to-analog conversion is easier than ADC, precoding strategies which move complexity to the transmitter are investigated. The use of time-interleaved ADCs to attain higher precision, and hence higher dynamic range, is considered for both singlecarrier and multicarrier systems. The approach is to design receiver algorithms that jointly address mismatch between the component ADCs and the channel dispersion.