EHCS: Dynamic Vertically Integrated Power-Performance-Reliability Modulation in Embedded Digital Signal Processors

严重的新技术挑战是微电子技术进步的障碍，因为技术规模遇到了材料性能和光刻的基本限制。随着微电子设备被缩小到原子尺寸，现在正在观察到巨大的工艺变化以及其他随机的性能和功率限制缺陷。这需要对电子设计中的模块级性能进行悲观的保护，以确保适当的整体系统级功能，迫使系统在远低于底层设计结构固有能力的性能水平下运行。此外，嵌入式DSP系统必须被设计为在由病态输入信号引起的最坏的操作条件下工作。未来技术中不断提高的性能和输入信号的可变性带来的更宽的保护带宽可能会抵消可伸缩带来的大部分性能优势，使摩尔？S定律对嵌入式系统的关键回报停滞不前。在这样的环境下，尽管存在这些不确定性，但只有将防护带控制在可接受的范围内，引入新的规模化设备才具有成本效益。这仍然是一个尚未解决的主要挑战，特别是对于必须同时优化系统级功率、性能和可靠性的嵌入式DSP处理器。为了解决这些问题，该项目正在开发测试、诊断和连续信号监控的概念，以实现静态(过程)和动态(输入信号)不确定性的动态电路-架构-算法协同调制(或协同调谐)。在这种新的设计模式下，反馈驱动的重构控制机制涉及电路和软件(调谐旋钮)。都被设计到IC中，以支持功率性能权衡和制造后的可靠性恢复。这项研究追求的是垂直集成的电路体系结构算法调整方法，这些方法比在设计层次的单个级别执行的优化提供10倍的好处。生成的诊断信息用于动态优化(制造后)单个模块级别的行为，以通过专门设计的硬件和软件控制机制优化系统级别的性能、功率和可靠性指标。通过这种方式，设计的每个实例化都能适应其在存在工艺变化和不利操作条件时所能达到的最高性能、功率和可靠性水平。从事该项目的研究生在这个多学科的研究中接受了一种独特的培训，这些研究结合了数字设计和测试、控制系统、嵌入式数字信号处理架构和算法等领域。这些学生参加企业的暑期实习项目。通过佐治亚理工学院、奥本大学和塔斯基吉大学的共同努力，该项目还积极支持招募更多美国公民、女性和少数族裔进入研究生课程的目标。

Serious new technical challenges are barriers to advances in microelectronics technology as technology scaling comes up against fundamental limits of material properties and lithography. Large process variations and other random performance and power constraining imperfections are now being observed as microelectronic devices are scaled down to atomic dimensions. This requires that module level performance in electronic designs be pessimistically guardbanded to ensure proper overall system level functionality, forcing systems to operate at performance levels far below the inherent capability of the underlying design fabric. In addition, embedded DSP systems must be designed to work under worst case operating conditions resulting from ill-conditioned input signals. Wider guardbands from increasing performance and input signal variability in future technologies can negate most of the performance benefits of scaling, stalling a key payoff from Moore?s Law for embedded systems. In such an environment, introduction of new scaled devices will be cost-effective only if the guardbands can be controlled down to acceptable margins, despite the presence of these uncertainties. This remains a major unsolved challenge, especially for embedded DSP processors that must be concurrently optimized for system level power, performance and reliability. To address these problems, this project is developing the concept of test, diagnosis and continuous signal monitoring enabled dynamic circuit-architecture-algorithm co-modulation (or co-tuning) for both static (procees) and dynamic (input signal) uncertainties. Under this new design paradigm, feedback driven reconfiguration control mechanisms involving circuitry and software (?tuning knobs?) are designed into the IC to support power-performance trade-off and reliability recovery post manufacture. The research pursues vertically integrated circuit-architecture-algorithm tuning methods that offer 10X benefits over optimizations performed at a single level of the design hierarchy. The diagnostic information generated is used to dynamically optimize (post-manufacture) individual module level behavior to optimize system level performance, power and reliability metrics via specially designed hardware and software control mechanisms. In this way, each instantiation of a design adapts to the maximum performance, power, and reliability levels it is capable of in the presence of process variations and adverse operating conditions. Graduate students working on the project receive a unique kind of training in this multidisciplinary research, which together the fields of digital design and test, control systems, embedded digital signal processing architectures, and algorithms. The students participate in summer internship programs with industry. Through joint efforts at Georgia Tech, Auburn University, and Tuskegee University, this project also actively supports the goals of recruiting more U.S. citizens, women and minorities to graduate programs.