SHF: Small: Targeting Hazard Activated Faults to Improve Open Defect Coverage of Scan Delay Tests

使用计算机管理日常生活方方面面的爆炸性增长，正迅速使我们严重依赖基础电子电路的可靠性。然而，如果出现故障或故障，这种对电子设备的广泛依赖可能会导致更大的中断、损害和经济损失。因此，集成电路(IC)制造商已经面临着对航空航天、汽车和植入式医疗设备等应用中使用的零部件的更严格的质量和可靠性要求；要求如此高质量的应用范围预计将在未来几年迅速扩大。不幸的是，以合理的成本以数量级提高IC的质量和可靠性是极具挑战性的，新材料、电路结构引发的新型制造缺陷和细微缺陷使这一点变得更加困难。本提案将介绍测试尖端微电子电路所需的技术，以确保无故障运行。该项目还将包括研究生和本科生培训，包括代表人数不足的群体的成员，从而有助于扩大信息和通信技术方面的劳动力。为了确保无故障运行，单个集成电路在安装到电子电路板和组装成系统之前，会经过广泛的测试。然而，验证现代IC中的数十亿个内部组件是否都是无缺陷的问题，由于可用于访问硅上的微型电路和组件的外部布线数量有限而变得更加复杂。通常，有缺陷的组件在运行期间激活并导致故障之前，可能会在IC内保持休眠和不使用几天甚至几个月。新的研究表明，这种测试逃逸的数量可能比之前认为的要多得多，因为存在一些特别难检测的开路缺陷，这些缺陷可能会被常见的电路危险激活。拟议研究的目的是开发和验证针对这些类型的制造缺陷的有针对性的、具有成本效益的测试方法。特别是，该项目将开发针对开放缺陷的强大测试策略，以显著减少缺陷部件和操作故障。它提出了四项活动来实现这一目标：i)针对复杂CMOS单元中的开路故障的常规扫描测试，ii)危险激活开路缺陷的测试生成，iii)危险激活开路检测的低成本设计为测试方法，以及iv)对最先进的电路和批量生产制造的结果进行验证。

The explosive growth in the use of computers to manage all aspects of everyday living is rapidly making us critically dependent on the reliability of the underlying electronic circuits. However, this extensive reliance on electronics may result in much greater disruption, damage and financial loss in case of malfunction or failure. Consequently, integrated circuit (IC) manufacturers are already facing far more stringent quality and reliability demands for parts used in applications such as aerospace, automotive, and implantable medical devices; the range of applications demanding such high quality is expected to expand rapidly in the next few years. Unfortunately, improving the quality and reliability of ICs by orders of magnitude at reasonable cost is extremely challenging, which is made even more difficult by new types of manufacturing flaws and subtle defects being triggered by the new materials, circuit structures. This proposal will address techniques needed for testing cutting edge microelectronic circuits so as to ensure failure free operation. The project will also involve graduate and undergraduate student training, include members of underrepresented groups and will thus help enlarge the workforce in information and communication technologies.To ensure failure free operation, individual integrated circuits are extensively tested before being incorporated into electronic circuit boards and assembled into systems. However, the problem of verifying that each of the billions of internal components in modern ICs is defect free is compounded by the limited number of external wires that are available to access the miniature circuits and components on silicon. Often a defective component can remain dormant and unused inside an IC for days, or even months, before it becomes activated during operation resulting in a malfunction. New research indicates that the number of such test escapes may be much larger than previously believed because of the presence of some particularly hard to detect open defects that can become activated by commonly occurring circuit hazards. The aim of the proposed research is to develop and validate targeted and cost effective test methodologies for precisely those types of manufacturing defects. In particular, the project will develop robust test strategies targeting open defects to significantly reduce Defective Parts per Million and operational failure. It proposes four activities to achieve this goal: i) conventional scan tests for targeting the open faults in complex CMOS cells, ii) test generation for hazard activated open defects, iii) low-cost design-for-test methods for hazard activated opens detection, and iv) validation of results on state-of-the-art circuits and volume production manufacturing.