SHF: Small: Targeting Hazard Activated Faults to Improve Open Defect Coverage of Scan Delay Tests

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The explosive growth in the use of computers to manage all aspects of everyday living is rapidly making us critically dependent on the reliability of the underlying electronic circuits. However, this extensive reliance on electronics may result in much greater disruption, damage and financial loss in case of malfunction or failure. Consequently, integrated circuit (IC) manufacturers are already facing far more stringent quality and reliability demands for parts used in applications such as aerospace, automotive, and implantable medical devices; the range of applications demanding such high quality is expected to expand rapidly in the next few years. Unfortunately, improving the quality and reliability of ICs by orders of magnitude at reasonable cost is extremely challenging, which is made even more difficult by new types of manufacturing flaws and subtle defects being triggered by the new materials, circuit structures. This proposal will address techniques needed for testing cutting edge microelectronic circuits so as to ensure failure free operation. The project will also involve graduate and undergraduate student training, include members of underrepresented groups and will thus help enlarge the workforce in information and communication technologies.To ensure failure free operation, individual integrated circuits are extensively tested before being incorporated into electronic circuit boards and assembled into systems. However, the problem of verifying that each of the billions of internal components in modern ICs is defect free is compounded by the limited number of external wires that are available to access the miniature circuits and components on silicon. Often a defective component can remain dormant and unused inside an IC for days, or even months, before it becomes activated during operation resulting in a malfunction. New research indicates that the number of such test escapes may be much larger than previously believed because of the presence of some particularly hard to detect open defects that can become activated by commonly occurring circuit hazards. The aim of the proposed research is to develop and validate targeted and cost effective test methodologies for precisely those types of manufacturing defects. In particular, the project will develop robust test strategies targeting open defects to significantly reduce Defective Parts per Million and operational failure. It proposes four activities to achieve this goal: i) conventional scan tests for targeting the open faults in complex CMOS cells, ii) test generation for hazard activated open defects, iii) low-cost design-for-test methods for hazard activated opens detection, and iv) validation of results on state-of-the-art circuits and volume production manufacturing.