SHF: Small: Targeting Hazard Activated Faults to Improve Open Defect Coverage of Scan Delay Tests

SHF：小型：针对危险激活的故障以提高扫描延迟测试的开放缺陷覆盖率

• 批准号: 1527049
• 负责人: Adit Singh
• 金额: $ 44.98万
• 依托单位: Auburn University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-06-15 至 2019-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1527049&HistoricalAwards=false
• 关键词: SHF; Small; Targeting; Hazard; Activated

The explosive growth in the use of computers to manage all aspects of everyday living is rapidly making us critically dependent on the reliability of the underlying electronic circuits. However, this extensive reliance on electronics may result in much greater disruption, damage and financial loss in case of malfunction or failure. Consequently, integrated circuit (IC) manufacturers are already facing far more stringent quality and reliability demands for parts used in applications such as aerospace, automotive, and implantable medical devices; the range of applications demanding such high quality is expected to expand rapidly in the next few years. Unfortunately, improving the quality and reliability of ICs by orders of magnitude at reasonable cost is extremely challenging, which is made even more difficult by new types of manufacturing flaws and subtle defects being triggered by the new materials, circuit structures. This proposal will address techniques needed for testing cutting edge microelectronic circuits so as to ensure failure free operation. The project will also involve graduate and undergraduate student training, include members of underrepresented groups and will thus help enlarge the workforce in information and communication technologies.To ensure failure free operation, individual integrated circuits are extensively tested before being incorporated into electronic circuit boards and assembled into systems. However, the problem of verifying that each of the billions of internal components in modern ICs is defect free is compounded by the limited number of external wires that are available to access the miniature circuits and components on silicon. Often a defective component can remain dormant and unused inside an IC for days, or even months, before it becomes activated during operation resulting in a malfunction. New research indicates that the number of such test escapes may be much larger than previously believed because of the presence of some particularly hard to detect open defects that can become activated by commonly occurring circuit hazards. The aim of the proposed research is to develop and validate targeted and cost effective test methodologies for precisely those types of manufacturing defects. In particular, the project will develop robust test strategies targeting open defects to significantly reduce Defective Parts per Million and operational failure. It proposes four activities to achieve this goal: i) conventional scan tests for targeting the open faults in complex CMOS cells, ii) test generation for hazard activated open defects, iii) low-cost design-for-test methods for hazard activated opens detection, and iv) validation of results on state-of-the-art circuits and volume production manufacturing.

使用计算机管理日常生活的各个方面的爆炸性增长迅速使我们严重依赖底层电子电路的可靠性。然而，这种对电子设备的广泛依赖可能会在发生故障或故障时造成更大的破坏、损害和经济损失。因此，集成电路（IC）制造商已经面临着对航空航天、汽车和植入式医疗设备等应用中所用部件的更严格的质量和可靠性要求;预计未来几年，要求如此高质量的应用范围将迅速扩大。不幸的是，以合理的成本将IC的质量和可靠性提高几个数量级是非常具有挑战性的，由于新材料、电路结构引发的新型制造缺陷和细微缺陷，这变得更加困难。本提案将讨论测试尖端微电子电路所需的技术，以确保无故障运行。该项目还将涉及研究生和本科生培训，包括代表性不足的群体的成员，从而将有助于扩大信息和通信技术的劳动力，为确保无故障运行，个别集成电路在被纳入电子电路板和组装成系统之前进行了广泛的测试。然而，验证现代IC中数十亿内部组件中的每一个都是无缺陷的问题，由于可用于访问硅上的微型电路和组件的外部导线数量有限而变得更加复杂。通常，有缺陷的组件可以在IC内保持休眠和未使用数天，甚至数月，然后在操作期间被激活，导致故障。新的研究表明，这种测试逃逸的数量可能比以前认为的要大得多，因为存在一些特别难以检测的开路缺陷，这些缺陷可能会被常见的电路危险激活。拟议的研究的目的是开发和验证有针对性的和成本效益的测试方法，正是这些类型的制造缺陷。特别是，该项目将开发针对开放缺陷的强大测试策略，以显著降低每百万个缺陷和操作故障。它提出了四个活动来实现这一目标：i）针对复杂CMOS单元中的开路故障的常规扫描测试，ii）针对危险激活开路缺陷的测试生成，iii）用于危险激活开路检测的低成本测试设计方法，以及iv）对最先进电路和批量生产制造的结果进行验证。